PIC18F67J11-IPT Datasheet, PDF (349/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
CPFSGT
Compare f with W, Skip if f > W
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
CPFSGT f {,a}
0 ≤ f ≤ 255
a ∈ [0,1]
(f) – (W),
skip if (f) > (W)
(unsigned comparison)
None
0110 010a ffff ffff
Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
No
operation
No
operation
Q2
No
operation
No
operation
Q3
No
operation
No
operation
Q4
No
operation
No
operation
Example:
HERE
CPFSGT REG, 0
NGREATER :
GREATER :
Before Instruction
PC
=
W
=
After Instruction
If REG
>
PC
=
If REG
≤
PC
=
Address (HERE)
?
W;
Address (GREATER)
W;
Address (NGREATER)
CPFSLT
Compare f with W, Skip if f < W
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
CPFSLT f {,a}
0 ≤ f ≤ 255
a ∈ [0,1]
(f) – (W),
skip if (f) < (W)
(unsigned comparison)
None
0110 000a ffff ffff
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
If skip:
Q1
Read
register ‘f’
Q2
Process
Data
Q3
No
operation
Q4
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
No
operation
Q1
No
operation
No
operation
Q2
No
operation
No
operation
Q3
No
operation
No
operation
Q4
No
operation
No
operation
Example:
HERE
NLESS
LESS
CPFSLT REG, 1
:
:
Before Instruction
PC
=
W
=
After Instruction
If REG
<
PC
=
If REG
≥
PC
=
Address (HERE)
?
W;
Address (LESS)
W;
Address (NLESS)
© 2009 Microchip Technology Inc.
DS39778D-page 349