PIC18F67J11-IPT Datasheet, PDF (78/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
TABLE 5-5: REGISTER FILE SUMMARY (PIC18F87J11 FAMILY) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on
Page:
FSR2H
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte ---- xxxx 58, 84
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx 58, 84
STATUS
—
—
—
N
OV
Z
DC
C
---x xxxx 58, 82
TMR0H
Timer0 Register High Byte
0000 0000 58, 181
TMR0L
Timer0 Register Low Byte
xxxx xxxx 58, 181
T0CON
OSCCON⁽²⁾/
REFOCON⁽³⁾
TMR0ON
IDLEN
ROON
T08BIT
IRCF2
—
T0CS
IRCF1
ROSSLP
T0SE
IRCF0
ROSEL
PSA
OSTS⁽⁴⁾
RODIV3
T0PS2
—
RODIV2
T0PS1
SCS1
RODIV1
T0PS0
SCS0
RODIV0
1111 1111
0110 q100
0-00 0000
58, 180
58, 34
58, 41
CM1CON
CON
COE
CPOL
EVPOL1 EVPOL0
CREF
CCH1
CCH0 0001 1111 58, 304
CM2CON
CON
COE
CPOL
EVPOL1 EVPOL0
CREF
CCH1
CCH0 0001 1111 58, 304
RCON
IPEN
—
CM
TMR1H⁽²⁾/
ODCON1⁽³⁾
TMR1L⁽²⁾/
ODCON2⁽³⁾
T1CON ⁽²⁾/
ODCON3⁽³⁾
TMR2⁽²⁾/
PADCFG1⁽³⁾
PR2⁽²⁾/
MEMCON^(3,7)
Timer1 Register High Byte
—
—
Timer1 Register Low Byte
—
—
RD16
T1RUN
—
—
Timer2 Register
—
—
Timer2 Period Register
EDBIS
—
—
—
T1CKPS1
—
—
WAIT1
RI
CCP5OD
—
T1CKPS0
—
—
WAIT0
TO
CCP4OD
—
T1OSCEN
—
—
—
PD
ECCP3OD
—
T1SYNC
—
—
—
POR
BOR 0-11 1100
xxxx xxxx
ECCP2OD ECCP1OD ---0 0000
xxxx xxxx
U2OD
U1OD ---- --00
TMR1CS TMR1ON 0000 0000
SPI2OD SPI1OD ---- --00
0000 0000
—
PMPTTL ---- ---0
1111 1111
WM1
WM0 0-00 --00
56, 58,
127
58, 184
58, 131
58, 184
58, 131
58, 184
58, 131
58, 189
58, 132
58, 189
58, 100
T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 58, 189
SSP1BUF
MSSP1 Receive Buffer/Transmit Register
SSP1ADD/ MSSP1 Address Register (I²C™ Slave mode), MSSP1 Baud Rate Reload Register (I²C Master mode)
SSP1MSK⁽⁵⁾
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
xxxx xxxx 58, 224,
233
0000 0000 58, 233
0000 0000 58, 240
SSP1STAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 58, 224,
234
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0 0000 0000 58, 225,
235
SSP1CON2
GCEN
GCEN
ACKSTAT ACKDT
ACKEN
RCEN
PEN
RSEN/
ACKSTAT ADMSK5⁽⁶⁾ ADMSK4⁽⁶⁾ ADMSK3⁽⁶⁾ ADMSK2⁽⁶⁾ ADMSK1⁽⁶⁾
SEN
SEN
0000 0000 58, 236,
270
ADRESH
A/D Result Register High Byte
xxxx xxxx 59, 293
ADRESL
ADCON0⁽²⁾/
ANCON1⁽³⁾
ADCON1⁽²⁾/
ANCON0⁽³⁾
A/D Result Register Low Byte
VCFG1
VCFG0
CHS3
PCFG15 PCFG14 PCFG13
ADFM
ADCAL
ACQT2
PCFG7
PCFG6
—
CHS2
PCFG12
ACQT1
PCFG4
CHS1
PCFG11
ACQT0
PCFG3
CHS0
PCFG10
ADCS2
PCFG2
GO/DONE
PCFG9
ADCS1
PCFG1
ADON
PCFG8
ADCS0
PCFG0
xxxx xxxx
0000 0000
0000 0000
0000 0000
00-0 0000
59, 293
59, 293
59, 295
59, 294
59, 295
WDTCON
REGSLP LVDSTAT
—
ADSHR
—
—
—
SWDTEN 0x-0 ---0 59, 323
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Bold indicates shared access SFRs.
Bit 21 of the PC is only available in Serial Programming modes.
Default (legacy) SFR at this address, available when WDTCON<4> = 0.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP modules are operating in I²C™ Slave mode. See Section 19.4.3.2
“Address Masking Modes” for details
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are unimplemented.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
DS39778D-page 78
© 2009 Microchip Technology Inc.