PIC18F67J11-IPT Datasheet, PDF (165/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
11.2.3.1 READ FROM SLAVE PORT
When chip select is active and a read strobe occurs
(PMCS = 1 and PMRD = 1), the data from one of the
four output bytes is presented onto PMD<7:0>. Which
byte is read depends on the 2-bit address placed on
ADDR<1:0>. Table 11-2 shows the corresponding
output registers and their associated address.
When an output buffer is read, the corresponding
OBxE bit is set. The OBE flag bit is set when all the buf-
fers are empty. If any buffer is already empty (OBxE =
1), the next read to that buffer will generate an OBUF
event.
FIGURE 11-7:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1 | Q2 | Q3 | Q4 | Q1 | Q2 | Q3 | Q4 | Q1 | Q2 | Q3 | Q4
PMCS
PMWR
PMRD
PMD<7:0>
PMA<1:0>
OBE
PMPIF
11.2.3.2 WRITE TO SLAVE PORT
When chip select is active and a write strobe occurs
(PMCS = 1 and PMWR = 1), the data from PMD<7:0>
is captured into one of the four input buffer bytes.
Which byte is written depends on the 2-bit address
placed on ADDRL<1:0>. Table 11-2 shows the corre-
sponding input registers and their associated address.
When an input buffer is written, the corresponding IBxF
bit is set. The IBF flag bit is set when all the buffers are
written. If any buffer is already written (IBxF = 1), the
next write strobe to that buffer will generate an OBUF
event and the byte will be discarded.
FIGURE 11-8:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1 | Q2 | Q3 | Q4 | Q1 | Q2 | Q3 | Q4 | Q1 | Q2 | Q3 | Q4
PMCS
PMWR
PMRD
PMD<7:0>
PMA<1:0>
IBF
PMPIF
© 2009 Microchip Technology Inc.
DS39778D-page 165