PIC18F67J11-IPT Datasheet, PDF(133/448 Page) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

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PIC18F67J11-IPT Datasheet, PDF (133/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

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PIC18F87J11 FAMILY

TABLE 10-4: PORTA FUNCTIONS

Pin Name

Function

TRIS

Setting

I/O

I/O

Type

Description

RA0/AN0

RA0

0

O

DIG LATA<0> data output; not affected by analog input.

1

I

TTL PORTA<0> data input; disabled when analog input enabled.

AN0

1

I

ANA A/D input channel 0. Default input configuration on POR; does not

affect digital output.

RA1/AN1

RA1

0

O

DIG LATA<1> data output; not affected by analog input.

1

I

TTL PORTA<1> data input; disabled when analog input enabled.

AN1

1

I

ANA A/D input channel 1. Default input configuration on POR; does not

affect digital output.

RA2/AN2/VREF-

RA2

0

O

DIG LATA<2> data output; not affected by analog input. Disabled when

CVREF output enabled.

1

I

TTL PORTA<2> data input. Disabled when analog functions enabled;

disabled when CVREF output enabled.

AN2

1

I

ANA A/D input channel 2. Default input configuration on POR; not affected

by analog output.

VREF-

1

I

ANA A/D low reference voltage input.

RA3/AN3/VREF+ RA3

0

O

DIG LATA<3> data output; not affected by analog input.

1

I

TTL PORTA<3> data input; disabled when analog input enabled.

AN3

1

I

ANA A/D input channel 3. Default input configuration on POR.

VREF+

1

I

ANA A/D high reference voltage input.

RA4/PMD5/

T0CKI/

RA4

0

1

PMD5(1)

x

O

DIG LATA<4> data output.

I

ST PORTA<4> data input; default configuration on POR.

O

DIG Parallel Master Port data output.

x

I

TTL Parallel Master Port data output.

T0CKI

x

I

ST Timer0 clock input.

RA5/PMD4/AN4 RA5

0

O

DIG LATA<5> data output; not affected by analog input.

1

PMD4(1)

x

I

TTL PORTA<5> data input; disabled when analog input enabled.

O

DIG Parallel Master Port data output.

x

I

TTL Parallel Master Port data output.

AN4

1

I

ANA A/D input channel 4. Default configuration on POR.

OSC2/CLKO/

OSC2

x

O

ANA Main oscillator feedback output connection (HS and HSPLL modes).

RA6

CLKO

x

O

DIG System cycle clock output, FOSC/4 (EC, ECPLL, INTIO1 and INTPLL1

modes).

RA6

0

O

DIG LATA<6> data output; disabled when FOSC2 Configuration bit is set.

1

I

TTL PORTA<6> data input; disabled when FOSC2 Configuration bit is set.

OSC1/CLKI/

OSC1

x

RA7

CLKI

x

I

ANA Main oscillator input connection (HS and HSPLL modes).

I

ANA Main external clock source input (EC and ECPLL modes).

RA7

0

O

DIG LATA<7> data output; disabled when FOSC2 Configuration bit is set.

1

I

TTL PORTA<7> data input; disabled when FOSC2 Configuration bit is set.

Legend:

Note 1:

O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,

TTL = TTL Buffer Input, x = Donât care (TRIS bit does not affect port direction or is overridden for this option).

Alternate PMP configuration when the PMPMX Configuration bit is â0â; available on 80-pin devices only.

Â© 2009 Microchip Technology Inc.

DS39778D-page 133

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