PIC18F67J11-IPT Datasheet, PDF (161/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
11.1.4
PMP MULTIPLEXING OPTIONS
(80-PIN DEVICES)
By default, the PMP and the external memory bus
multiplex some of their signals to the same I/O pins on
PORTD and PORTE. It is possible that some applica-
tions may require the PMP signals to be located
elsewhere. For these instances, the 80-pin devices can
be configured to multiplex the PMP to different I/O
ports. PMP configuration is determined by the PMPMX
Configuration bit setting; by default, the PMP and EMB
modules share PORTD and PORTE. The optional pin
configuration is shown in Table 11-1.
TABLE 11-1: PMP PIN MULTIPLEXING FOR
80-PIN DEVICES
PMP Function
Pin Assignment
PMPMX = 1 PMPMX = 0
PMD0
PMD1
PMD2
PMD3
PORTD<0>
PORTD<1>
PORTD<2>
PORTD<3>
PORTF<7>
PORTF<6>
PORTF<5>
PORTH<4>
PMD4
PMD5
PMD6
PMD7
PMBE
PMWR
PMRD
PORTD<4>
PORTD<5>
PORTD<6>
PORTD<7>
PORTE<2>
PORTE<1>
PORTE<0>
PORTA<5>
PORTA<4>
PORTH<3>
PORTH<2>
PORTH<5>
PORTH<7>
PORTH<6>
11.2 Slave Port Modes
The primary mode of operation for the module is con-
figured using the MODE1:MODE0 bits in the
PMMODEH register. The setting affects whether the
module acts as a slave or a master and it determines
the usage of the control pins.
11.2.1 LEGACY MODE (PSP)
In Legacy mode (PMMODEH<1:0> = 00 and
PMPEN = 1), the module is configured as a Parallel
Slave Port with the associated enabled module pins
dedicated to the module. In this mode, an external
device, such as another microcontroller or micropro-
cessor, can asynchronously read and write data using
the 8-bit data bus (PMD<7:0>), the read (PMRD), write
(PMWR) and chip select (PMCS1) inputs. It acts as a
slave on the bus and responds to the read/write control
signals.
Figure 11-2 shows the connection of the Parallel Slave
Port. When chip select is active and a write strobe
occurs (PMCS = 1 and PMWR = 1), the data from
PMD<7:0> is captured into the PMDIN1L register.
FIGURE 11-2:
LEGACY PARALLEL SLAVE PORT EXAMPLE
Master
PMD<7:0>
PIC18 Slave
PMD<7:0>
PMCS
PMRD
PMWR
PMCS1
PMRD
PMWR
Address Bus
Data Bus
Control Lines
© 2009 Microchip Technology Inc.
DS39778D-page 161