PIC18F67J11-IPT Datasheet, PDF (143/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
TABLE 10-12: PORTE FUNCTIONS (CONTINUED)
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RE5/AD13/
RE5
0
PMA11/P1C
1
AD13⁽³⁾
x
x
PMA11
x
P1C⁽¹⁾
0
O
DIG LATE<5> data output.
I
ST PORTE<5> data input.
O
DIG External memory interface, address/data bit 13 output.⁽²⁾
I
TTL External memory interface, data bit 13 input.⁽²⁾
O
DIG Parallel Master Port address.
O
DIG ECCP1 Enhanced PWM output, channel C; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE6/AD14/
RE6
0
PMA10/P1B
1
AD14⁽³⁾
x
x
PMA10
x
P1B⁽¹⁾
0
O
DIG LATE<6> data output.
I
ST PORTE<6> data input.
O
DIG External memory interface, address/data bit 14 output.⁽²⁾
I
TTL External memory interface, data bit 14 input.⁽²⁾
O
DIG Parallel Master Port address.
O
DIG ECCP1 Enhanced PWM output, channel B; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE7/AD15/
RE7
0
PMA9/ECCP2/
1
P2A
AD15⁽³⁾
x
x
PMA9
x
ECCP2⁽⁴⁾
0
O
DIG LATE<7> data output.
I
ST PORTE<7> data input.
O
DIG External memory interface, address/data bit 15 output.⁽²⁾
I
TTL External memory interface, data bit 15 input.⁽²⁾
O
DIG Parallel Master Port address.
O
DIG ECCP2 compare output and ECCP2 PWM output; takes priority over
port data.
1
P2A⁽⁴⁾
0
I
ST ECCP2 capture input.
O
DIG ECCP2 Enhanced PWM output, channel A; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Legend:
Note 1:
2:
3:
4:
5:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin devices only).
External memory interface I/O takes priority over all other digital and PMP I/O.
Available on 80-pin devices only.
Alternate assignment for ECCP2/P2A when ECCP2MX Configuration bit is cleared (all devices in Microcontroller mode).
Default configuration for PMP (PMPMX Configuration bit = 1).
TABLE 10-13: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PORTE
RE7
RE6
RE5
RE4
LATE
LATE7 LATE6 LATE5 LATE4
TRISE
PORTG
TRISE7 TRISE6 TRISE5 TRISE4
RDPU
REPU RJPU⁽¹⁾
RG4
Legend: Shaded cells are not used by PORTE.
Note 1: Unimplemented on 64-pin devices, read as ‘0’.
RE3
LATE3
TRISE3
RG3
RE2
LATE2
TRISE2
RG2
RE1
LATE1
TRISE1
RG1
Bit 0
Reset
Values
on Page:
RE0
61
LATE0
60
TRISE0
60
RG0
61
© 2009 Microchip Technology Inc.
DS39778D-page 143