PIC18F67J11-IPT Datasheet, PDF (232/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
TABLE 19-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
57
PIR1
PMPIF
ADIF
RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
60
PIE1
PMPIE
ADIE
RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
60
IPR1
PMPIP
ADIP
RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
60
PIR3
SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF
60
PIE3
SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE
60
IPR3
SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP
60
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
60
TRISD
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0
60
TRISF
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2
—
—
60
SSP1BUF MSSP1 Receive Buffer/Transmit Register
58
SSPxCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 58, 61
SSPxSTAT SMP
CKE
D/A
P
S
R/W
UA
BF
58, 61
SSP2BUF MSSP2 Receive Buffer/Transmit Register
61
ODCON3⁽¹⁾
—
—
—
—
—
—
SPI2OD SPI1OD
58
Legend: Shaded cells are not used by the MSSP module in SPI mode.
Note 1: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
DS39778D-page 232
© 2009 Microchip Technology Inc.