PIC18F67J11-IPT Datasheet, PDF (22/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
TABLE 1-4: PIC18F8XJ1X PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number _{Pin Buffer}
80-TQFP ^{Type Type}
Description
MCLR
9
I
ST Master Clear (Reset) input. This pin is an active-low Reset to
the device.
OSC1/CLKI/RA7
OSC1
CLKI
RA7
49
Oscillator crystal or external clock input. Available only in
external oscillator modes (EC/ECPLL and HS/HSPLL).
I
ST Main oscillator input connection.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS
otherwise.
I CMOS Main clock input connection.
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
I/O TTL General purpose I/O pin. Available only in INTIO2 and
INTPLL2 Oscillator modes.
OSC2/CLKO/RA6
OSC2
CLKO
RA6
50
Oscillator crystal or clock output. Available only in external
oscillator modes (EC/ECPLL and HS/HSPLL).
O
— Main oscillator feedback output connection.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
O
— System cycle clock output (FOSC/4).
In EC, ECPLL, INTIO1 and INTPLL1 Oscillator modes,
OSC2 pin outputs CLKO which has 1/4 the frequency
of OSC1 and denotes the instruction cycle rate.
I/O TTL General purpose I/O pin. Available only in INTIO and INTPLL
Oscillator modes.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I = Input
O
= Output
P = Power
OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Default assignment for PMP data and control pins when PMPMX Configuration bit is set.
7: Alternate assignment for PMP data and control pins when PMPMX Configuration bit is cleared (programmed).
DS39778D-page 22
© 2009 Microchip Technology Inc.