PIC18F67J11-IPT Datasheet, PDF (130/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
Table 10-2 summarizes the output capabilities of the
ports. Refer to the “Absolute Maximum Ratings” in
Section 27.0 “Electrical Characteristics” for more
details.
TABLE 10-2: OUTPUT DRIVE LEVELS
Port
Drive
Description
PORTA Minimum Intended for indication.
PORTF
PORTG
PORTH⁽¹⁾
PORTD
PORTE
PORTJ⁽¹⁾
Medium Sufficient drive levels for
external memory interfacing
as well as indication.
PORTB
PORTC
High Suitable for direct LED drive
levels.
Note 1: These ports are not available on 64-pin
devices.
10.1.3 PULL-UP CONFIGURATION
Four of the I/O ports (PORTB, PORTD, PORTE and
PORTJ) implement configurable weak pull-ups on all
pins. These are internal pull-ups that allow floating
digital input signals to be pulled to a consistent level,
without the use of external resistors.
The pull-ups are enabled with a single bit for each of the
ports: RBPU (INTCON2<7>) for PORTB, and RDPU,
REPU and RJPU (PORTG<7:5>) for the other ports.
10.1.4 OPEN-DRAIN OUTPUTS
The output pins for several peripherals are also
equipped with a configurable, open-drain output option.
This allows the peripherals to communicate with
external digital logic operating at a higher voltage level,
without the use of level translators.
The open-drain option is implemented on port pins spe-
cifically associated with the data and clock outputs of
the EUSARTs, the MSSP modules (in SPI mode) and
the CCP and ECCP modules. It is selectively enabled
by setting the open-drain control bit for the correspond-
ing module in the ODCON registers (Register 10-1,
Register 10-2 and Register 10-3). Their configuration
is discussed in more detail with the individual port
where these peripherals are multiplexed.
The ODCON registers all reside in the SFR configuration
space and share the same SFR addresses as the Timer1
registers (see Section 5.3.4.1 “Shared Address SFRs”
for more details). The ODCON registers are accessed by
setting the ADSHR bit (WDTCON<4>).
When the open-drain option is required, the output pin
must also be tied through an external pull-up resistor
provided by the user to a higher voltage level, up to 5V
on digital only pins (Figure 10-2). When a digital logic
high signal is output, it is pulled up to the higher voltage
level.
FIGURE 10-2:
USING THE OPEN-DRAIN
OUTPUT (EUSARTx
SHOWN AS EXAMPLE)
3.3V
+5V
PIC18F87J11
VDD
TXX ^3.3V
5V
(at logic ‘1’)
10.1.5 TTL INPUT BUFFER OPTION
Many of the digital I/O ports use Schmitt Trigger (ST)
input buffers. While this form of buffering works well
with many types of input, some applications may
require TTL-level signals to interface with external logic
devices. This is particularly true with the EMB and the
Parallel Master Port (PMP), which are particularly likely
to be interfaced to TTL-level logic or memory devices.
The inputs for the PMP can be optionally configured for
TTL buffers with the PMPTTL bit in the PADCFG1 reg-
ister (Register 10-4). Setting this bit configures all data
and control input pins for the PMP to use TTL buffers.
By default, these PMP inputs use the port’s ST buffers.
As with the ODCON registers, the PADCFG1 register
resides in the SFR configuration space; it shares the
same memory address as the TMR2 register.
PADCFG1 is accessed by setting the ADSHR bit
(WDTCON<4>).
DS39778D-page 130
© 2009 Microchip Technology Inc.