PIC18F67J11-IPT Datasheet, PDF (270/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
TABLE 19-4: REGISTERS ASSOCIATED WITH I²C™ OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE TMR0IF INT0IF RBIF
57
PIR1
PMPIF
ADIF
RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60
PIE1
PMPIE ADIE
RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60
IPR1
PMPIP ADIP
RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60
PIR2
OSCFIF CM2IF CM1IF
—
BCL1IF LVDIF TMR3IF CCP2IF 60
PIE2
OSCFIE CM2IE CM1IE
—
BCL1IE LVDIE TMR3IE CCP2IE 60
IPR2
OSCFIP CM2IP CM1IP
—
BCL1IP LVDIP TMR3IP CCP2IP 60
PIR3
SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 60
PIE3
SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 60
IPR3
SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 60
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60
TRISD
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 60
SSP1BUF MSSP1 Receive Buffer/Transmit Register
58
SSP1ADD MSSP1 Address Register (I²C™ Slave mode),
58
MSSP1 Baud Rate Reload Register (I²C Master mode)
SSP1MSK⁽¹⁾ MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1 MSK0
58
SSP1CON1 WCOL SSPOV SSPEN
CKP
SSPM3 SSPM2 SSPM1 SSPM0 58
SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN
PEN
RSEN
SEN
58
GCEN ACKSTAT ADMSK5⁽²⁾ ADMSK4⁽²⁾ ADMSK3⁽²⁾ ADMSK2⁽²⁾ ADMSK1⁽²⁾ SEN
SSP1STAT SMP
CKE
D/A
P
S
R/W
UA
BF
58
SSP2BUF MSSP2 Receive Buffer/Transmit Register
61
SSP2ADD MSSP2 Address Register (I²C Slave mode),
61
MSSP2 Baud Rate Reload Register (I²C Master mode)
SSP2MSK⁽¹⁾ MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1 MSK0
61
SSP2CON1 WCOL SSPOV SSPEN
CKP
SSPM3 SSPM2 SSPM1 SSPM0 61
SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN
PEN
RSEN
SEN
61
GCEN ACKSTAT ADMSK5⁽²⁾ ADMSK4⁽²⁾ ADMSK3⁽²⁾ ADMSK2⁽²⁾ ADMSK1⁽²⁾ SEN
SSP2STAT SMP
CKE
D/A
P
S
R/W
UA
BF
61
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I²C™ mode.
Note 1: SSPxMSK shares the same address in SFR space as SSPxADD, but is only accessible in certain I²C™
Slave operating modes in 7-bit Masking mode. See Section 19.4.3.4 “7-Bit Address Masking Mode” for
more details.
2: Alternate bit definitions for use in I²C Slave mode operations only.
DS39778D-page 270
© 2009 Microchip Technology Inc.