PIC18F67J11-IPT Datasheet, PDF (175/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
11.4 Application Examples
This section introduces some potential applications for
the PMP module.
11.4.1
MULTIPLEXED MEMORY OR
PERIPHERAL
Figure 11-27 demonstrates the hookup of a memory or
other addressable peripheral in Full Multiplex mode.
Consequently, this mode achieves the best pin saving
from the microcontroller perspective. However, for this
configuration, there needs to be some external latches
to maintain the address.
FIGURE 11-27: EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATION
PIC18F
PMD<7:0>
PMALL
PMALH
PMCS
PMRD
PMWR
373 ^A<7:0>
D<7:0>
A<15:8>
373
A<15:0>
D<7:0>
CE
OE WR
Address Bus
Data Bus
Control Lines
11.4.2
PARTIALLY MULTIPLEXED
MEMORY OR PERIPHERAL
Partial multiplexing implies using more pins; however,
for a few extra pins, some extra performance can be
achieved. Figure 11-28 shows an example of a mem-
ory or peripheral that is partially multiplexed with an
external latch. If the peripheral has internal latches as
shown in Figure 11-29, then no extra circuitry is
required except for the peripheral itself.
FIGURE 11-28: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION
PIC18F
PMD<7:0>
PMALL
PMA<14:7>
PMCS
PMRD
PMWR
373
A<14:8>
A<7:0>
D<7:0>
A<14:0>
D<7:0>
CE
OE WR
Address Bus
Data Bus
Control Lines
FIGURE 11-29: EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION
PIC18F
PMD<7:0>
PMALL
PMCS
PMRD
PMWR
Parallel Peripheral
AD<7:0>
ALE
CS
RD
WR
Address Bus
Data Bus
Control Lines
© 2009 Microchip Technology Inc.
DS39778D-page 175