PIC18F67J11-IPT Datasheet, PDF (323/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
24.2 Watchdog Timer (WDT)
For PIC18F87J11 Family devices, the WDT is driven by
the INTRC oscillator. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period
is 4 ms and has the same stability as the INTRC
oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexor, controlled by the WDTPS bits
in Configuration Register 2H. Available periods range
from about 4 ms to 135 seconds (2.25 minutes
depending on voltage, temperature and WDT post-
scaler). The WDT and postscaler are cleared whenever
a SLEEP or CLRWDT instruction is executed, or a clock
failure (primary or Timer1 oscillator) has occurred.
FIGURE 24-1:
WDT BLOCK DIAGRAM
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
2: When a CLRWDT instruction is executed,
the postscaler count will be cleared.
24.2.1 CONTROL REGISTER
The WDTCON register (Register 24-9) is a readable
and writable register. The SWDTEN bit enables or dis-
ables WDT operation. This allows software to override
the WDTEN Configuration bit and enable the WDT only
if it has been disabled by the Configuration bit.
The ADSHR bit selects which SFRs are currently
selected and accessible. See Section 5.3.4.1 “Shared
Address SFRs” for additional details.
The LVDSTAT is a read-only status bit which is continu-
ously updated and provides information about the current
level of VDDCORE. This bit is only valid when the on-chip
voltage regulator is enabled.
SWDTEN
INTRC Oscillator
CLRWDT
All Device Resets
WDTPS3:WDTPS0
Sleep
Enable WDT
INTRC Control
WDT Counter
÷128
Programmable Postscaler Reset
1:1 to 1:32,768
WDT
4
Wake-up from
Power-Managed
Modes
WDT
Reset
© 2009 Microchip Technology Inc.
DS39778D-page 323