PIC18F67J11-IPT Datasheet, PDF (442/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
Bit Status During Initialization .................................... 56
Reader Response ............................................................ 434
Reference Clock Output ..................................................... 40
Register File ....................................................................... 74
Register File Summary ................................................. 77–81
Registers
ADCON0 (A/D Control 0) ......................................... 293
ADCON0 (A/D Control 1) ......................................... 294
ANCON0 (A/D Port Configuration 2) ........................ 295
ANCON1 (A/D Port Configuration 1) ........................ 295
BAUDCONx (Baud Rate Control) ............................ 274
CCPxCON (Capture/Compare/PWM Control) ......... 197
CCPxCON (ECCPx Control) .................................... 205
CMSTAT (Comparator Output Status) ..................... 305
CMxCON (Comparatorx Control) ............................. 304
CONFIG1H (Configuration 1 High) .......................... 317
CONFIG1L (Configuration 1 Low) ............................ 317
CONFIG2H (Configuration 2 High) .......................... 319
CONFIG3H (Configuration 3 High) .......................... 321
CONFIG3L (Configuration 3 Low) ...................... 65, 320
CVRCON (Comparator Voltage Reference Control) 312
DEVID1 (Device ID 1) .............................................. 322
DEVID2 (Device ID 2) .............................................. 322
ECCPxAS (ECCPx Auto-Shutdown Control) ........... 218
ECCPxDEL (ECCPx PWM Delay) ........................... 218
EECON1 (EEPROM Control 1) .................................. 91
INTCON (Interrupt Control) ...................................... 115
INTCON2 (Interrupt Control 2) ................................. 116
INTCON3 (Interrupt Control 3) ................................. 117
IPR1 (Peripheral Interrupt Priority 1) ........................ 124
IPR2 (Peripheral Interrupt Priority 2) ........................ 125
IPR3 (Peripheral Interrupt Priority 3) ........................ 126
MEMCON (External Memory Bus Control) .............. 100
ODCON1 (Peripheral Open-Drain Control 1) ........... 131
ODCON2 (Peripheral Open-Drain Control 2) ........... 131
ODCON3 (Peripheral Open-Drain Control 3) ........... 131
OSCCON (Oscillator Control) .................................... 34
OSCTUNE (Oscillator Tuning) ................................... 35
PADCFG1 (I/O Pad Configuration Control) ............. 132
PIE1 (Peripheral Interrupt Enable 1) ........................ 121
PIE2 (Peripheral Interrupt Enable 2) ........................ 122
PIE3 (Peripheral Interrupt Enable 3) ........................ 123
PIR1 (Peripheral Interrupt Request (Flag) 1) ........... 118
PIR2 (Peripheral Interrupt Request (Flag) 2) ........... 119
PIR3 (Peripheral Interrupt Request (Flag) 3) ........... 120
PMADDRH (Parallel Port Address High Byte, Master
Mode Only) ...................................................... 160
PMCONH (Parallel Port Control High Byte) ............. 154
PMCONL (Parallel Port Control Low Byte) .............. 155
PMEH (Parallel Port Enable High Byte) ................... 157
PMEL (Parallel Port Enable Low Byte) .................... 158
PMMODEH (Parallel Port Mode High Byte) ............. 156
PMMODEL (Parallel Port Mode Low Byte) .............. 157
PMSTAT (Parallel Port Status High Byte) ................ 158
PMSTAT (Parallel Port Status Low Byte) ................ 159
RCON (Reset Control) ....................................... 52, 127
RCSTAx (Receive Status and Control) .................... 273
REFOCON (Reference Oscillator Control) ................. 41
SSPCON2 (MSSPx Control 2, I²C Master Mode) .... 236
SSPCON2 (MSSPx Control 2, I²C Slave Mode) ...... 237
SSPxCON1 (MSSPx Control 1, I²C Mode) .............. 235
SSPxCON1 (MSSPx Control 1, SPI Mode) ............. 225
SSPxMSK (I²C Slave Address Mask) ...................... 237
SSPxSTAT (MSSPx Status, I²C Mode) ................... 234
SSPxSTAT (MSSPx Status, SPI Mode) .................. 224
DS39778D-page 442
STATUS .................................................................... 82
STKPTR (Stack Pointer) ............................................ 68
T0CON (Timer0 Control) ......................................... 179
T1CON (Timer1 Control) ......................................... 183
T2CON (Timer2 Control) ......................................... 189
T3CON (Timer3 Control) ......................................... 191
T4CON (Timer4 Control) ......................................... 195
TXSTAx (Transmit Status and Control) ................... 272
WDTCON (Watchdog Timer Control) ................ 76, 324
RESET ............................................................................. 361
Reset ................................................................................. 51
Brown-out Reset (BOR) ............................................. 51
Configuration Mismatch (CM) .................................... 51
MCLR Reset, During Power-Managed Modes .......... 51
MCLR Reset, Normal Operation ................................ 51
Power-on Reset (POR) .............................................. 51
RESET Instruction ..................................................... 51
Stack Full Reset ......................................................... 51
Stack Underflow Reset .............................................. 51
Watchdog Timer (WDT) Reset .................................. 51
Resets .............................................................................. 315
Brown-out Reset (BOR) ........................................... 315
Oscillator Start-up Timer (OST) ............................... 315
Power-on Reset (POR) ............................................ 315
Power-up Timer (PWRT) ......................................... 315
RETFIE ............................................................................ 362
RETLW ............................................................................ 362
RETURN .......................................................................... 363
Revision History ............................................................... 431
RLCF ............................................................................... 363
RLNCF ............................................................................. 364
RRCF ............................................................................... 364
RRNCF ............................................................................ 365
S
SCKx ................................................................................ 223
SDIx ................................................................................. 223
SDOx ............................................................................... 223
SEC_IDLE Mode ............................................................... 48
SEC_RUN Mode ................................................................ 44
Serial Clock, SCKx .......................................................... 223
Serial Data In (SDIx) ........................................................ 223
Serial Data Out (SDOx) ................................................... 223
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 365
Slave Select (SSx) ........................................................... 223
SLEEP ............................................................................. 366
Software Simulator (MPLAB SIM) ................................... 382
Special Event Trigger. See Compare (ECCP Module).
Special Features of the CPU ........................................... 315
Special Function Registers
Shared Registers ....................................................... 76
SPI Mode (MSSP) ........................................................... 223
Associated Registers ............................................... 232
Bus Mode Compatibility ........................................... 231
Clock Speed, Interactions ........................................ 231
Effects of a Reset .................................................... 231
Enabling SPI I/O ...................................................... 227
Master Mode ............................................................ 228
Master/Slave Connection ......................................... 227
Operation ................................................................. 226
Operation in Power-Managed Modes ...................... 231
Serial Clock .............................................................. 223
Serial Data In ........................................................... 223
Serial Data Out ........................................................ 223
Slave Mode .............................................................. 229
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