PIC18F67J11-IPT Datasheet, PDF (443/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
Slave Select ............................................................. 223
Slave Select Synchronization .................................. 229
SPI Clock ................................................................. 228
SSPxBUF Register .................................................. 228
SSPxSR Register ..................................................... 228
Typical Connection .................................................. 227
SSPOV ............................................................................. 259
SSPOV Status Flag ......................................................... 259
SSPxSTAT Register
R/W Bit ............................................................. 238, 241
SSx .................................................................................. 223
Stack Full/Underflow Resets .............................................. 69
SUBFSR .......................................................................... 377
SUBFWB .......................................................................... 366
SUBLW ............................................................................ 367
SUBULNK ........................................................................ 377
SUBWF ............................................................................ 367
SUBWFB .......................................................................... 368
SWAPF ............................................................................ 368
T
Table Pointer Operations (table) ........................................ 92
Table Reads/Table Writes ................................................. 69
TBLRD ............................................................................. 369
TBLWT ............................................................................. 370
Timer0 .............................................................................. 179
Associated Registers ............................................... 181
Operation ................................................................. 180
Overflow Interrupt .................................................... 181
Prescaler .................................................................. 181
Switching Assignment ...................................... 181
Prescaler Assignment (PSA Bit) .............................. 181
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 181
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 180
Source Edge Select (T0SE Bit) ................................ 180
Source Select (T0CS Bit) ......................................... 180
Timer1 .............................................................................. 183
16-Bit Read/Write Mode ........................................... 185
Associated Registers ............................................... 188
Considerations in Asynchronous Counter Mode ...... 187
Interrupt .................................................................... 186
Operation ................................................................. 184
Oscillator .......................................................... 183, 185
Layout Considerations ..................................... 185
Oscillator, as Secondary Clock .................................. 35
Resetting, Using the ECCPx Special Event Trigger 186
Special Event Trigger (ECCP) ................................. 209
TMR1H Register ...................................................... 183
TMR1L Register ....................................................... 183
Use as a Clock Source ............................................ 185
Use as a Real-Time Clock ....................................... 186
Timer2 .............................................................................. 189
Associated Registers ............................................... 190
Interrupt .................................................................... 190
Operation ................................................................. 189
Output ...................................................................... 190
PR2 Register ............................................................ 210
TMR2 to PR2 Match Interrupt .................................. 210
Timer3 .............................................................................. 191
16-Bit Read/Write Mode ........................................... 193
Associated Registers ............................................... 193
Operation ................................................................. 192
Oscillator .......................................................... 191, 193
Overflow Interrupt ............................................ 191, 193
Special Event Trigger (ECCPx) ............................... 193
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TMR3H Register ...................................................... 191
TMR3L Register ...................................................... 191
Timer4 ............................................................................. 195
Associated Registers ............................................... 196
Operation ................................................................. 195
Output ...................................................................... 196
Postscaler. See Postscaler, Timer4.
PR4 Register ........................................................... 195
Prescaler. See Prescaler, Timer4.
TMR4 Register ........................................................ 195
TMR4 to PR4 Match Interrupt .......................... 195, 196
Timing Diagrams
A/D Conversion ....................................................... 422
Asynchronous Reception ......................................... 284
Asynchronous Transmission ................................... 282
Asynchronous Transmission (Back to Back) ........... 282
Automatic Baud Rate Calculation ............................ 280
Auto-Wake-up Bit (WUE) During Normal Operation 285
Auto-Wake-up Bit (WUE) During Sleep ................... 285
Baud Rate Generator with Clock Arbitration ............ 256
BRG Overflow Sequence ........................................ 280
BRG Reset Due to SDAx Arbitration During Start Condi-
tion ................................................................... 266
Bus Collision During a Repeated Start Condition (Case
1) ..................................................................... 267
Bus Collision During a Repeated Start Condition (Case
2) ..................................................................... 268
Bus Collision During a Start Condition (SCLx = 0) .. 266
Bus Collision During a Stop Condition (Case 1) ...... 269
Bus Collision During a Stop Condition (Case 2) ...... 269
Bus Collision During Start Condition (SDAx Only) .. 265
Bus Collision for Transmit and Acknowledge .......... 264
Capture/Compare/PWM (Including ECCP Modules) 412
CLKO and I/O .......................................................... 404
Clock Synchronization ............................................. 249
Clock/Instruction Cycle .............................................. 70
EUSART Synchronous Receive (Master/Slave) ...... 421
EUSART Synchronous Transmission (Master/Slave) ...
421
Example SPI Master Mode (CKE = 0) ..................... 413
Example SPI Master Mode (CKE = 1) ..................... 414
Example SPI Slave Mode (CKE = 0) ....................... 415
Example SPI Slave Mode (CKE = 1) ....................... 416
External Clock (All Modes Except PLL) ................... 402
External Memory Bus for Sleep (Extended Microcon-
troller Mode) ............................................ 106, 108
External Memory Bus for TBLRD (Extended Microcon-
troller Mode) ............................................ 106, 108
Fail-Safe Clock Monitor ........................................... 328
First Start Bit Timing ................................................ 257
Full-Bridge PWM Output .......................................... 214
Half-Bridge PWM Output ......................................... 213
I²C Acknowledge Sequence .................................... 262
I²C Bus Data ............................................................ 417
I²C Bus Start/Stop Bits ............................................ 417
I²C Master Mode (7 or 10-Bit Transmission) ........... 260
I²C Master Mode (7-Bit Reception) ......................... 261
I²C Slave Mode (10-Bit Reception, SEN = 0, ADMSK =
01001) ............................................................. 245
I²C Slave Mode (10-Bit Reception, SEN = 0) .......... 246
I²C Slave Mode (10-Bit Reception, SEN = 1) .......... 251
I²C Slave Mode (10-Bit Transmission) .................... 247
I²C Slave Mode (7-bit Reception, SEN = 0, ADMSK =
01011) ............................................................. 243
I²C Slave Mode (7-Bit Reception, SEN = 0) ............ 242
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