PIC18F67J11-IPT Datasheet, PDF (177/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
TABLE 11-3: REGISTERS ASSOCIATED WITH PMP MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE TMR0IF INT0IF
RBIF
57
PIR1
PMPIF
ADIF
RC1IF
TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
60
PIE1
PMPIE
ADIE
RC1IE
TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
60
IPR1
PMPIP
ADIP
RC1IP
TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
60
PMCONH
PMPEN
—
PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN
62
PMCONL
CSF1
CSF0
ALP
CS2P
CS1P
BEP
WRSP RDSP
62
PMADDRH/
CS2
CS1
Parallel Master Port Address High Byte
62
PMDOUT1H⁽¹⁾
Parallel Port Out Data High Byte (Buffer 1)
62
PMADDRL/
Parallel Master Port Address Low Byte
62
PMDOUT1L⁽¹⁾
Parallel Port Out Data Low Byte (Buffer 0)
62
PMDOUT2H
Parallel Port Out Data High Byte (Buffer 3)
62
PMDOUT2L
Parallel Port Out Data Low Byte (Buffer 2)
62
PMDIN1H
Parallel Port In Data High Byte (Buffer 1)
62
PMDIN1L
Parallel Port In Data Low Byte (Buffer 0)
62
PMDIN2H
Parallel Port In Data High Byte (Buffer 3)
62
PMDIN2L
Parallel Port In Data Low Byte (Buffer 2)
62
PMMODEH
BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0
62
PMMODEL
WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0
62
PMEH
PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8
62
PMEL
PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0
62
PMSTATH
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
62
PMSTATL
OBE
OBUF
—
PADCFG1⁽²⁾
—
—
—
—
OB3E
OB2E
OB1E
OB0E
62
—
—
—
—
PMPTTL
58
Legend:
Note 1:
2:
— = unimplemented, read as ‘0’. Shaded cells are not used during PMP operation.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and
addresses, but have different functions determined by the module’s operating mode.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
© 2009 Microchip Technology Inc.
DS39778D-page 177