PIC18F67J11-IPT Datasheet, PDF (146/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
TABLE 10-15: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
PORTF
RF7
RF6
RF5
RF4
RF3
RF2
RF1
—
61
LATF
LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1
—
60
TRISF
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1
—
60
ANCON0⁽¹⁾ PCFG7 PCFG6
—
PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
59
ANCON1⁽¹⁾ PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8
59
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF.
Note 1: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
10.8 PORTG, TRISG and
LATG Registers
PORTG is a 5-bit wide, bidirectional port. All pins on
PORTG are digital only and tolerate voltages up to
5.5V.
PORTG is multiplexed with EUSART2 functions
(Table 10-16). PORTG pins have Schmitt Trigger input
buffers. PORTG is also multiplexed with address and
control functions of the Parallel Master Port.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings. The pin override value is not loaded into
the TRIS register. This allows read-modify-write of the
TRIS register without concern due to peripheral
overrides.
Although the port itself is only five bits wide,
PORTG<7:5> bits are still implemented. These are
used to control the weak pull-ups on the I/O ports asso-
ciated with the external memory bus (PORTD, PORTE
and PORTJ). Setting these bits enables the pull-ups.
Since these are control bits and are not associated with
port I/O, the corresponding TRISG and LATG bits are
not implemented.
EXAMPLE 10-7: INITIALIZING PORTG
CLRF
CLRF
MOVLW
MOVWF
PORTG
LATG
04h
TRISG
; Initialize PORTG by
; clearing output
; data latches
; Alternate method to clear
; output data latches
; Value used to initialize
; data direction
; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as outputs
DS39778D-page 146
© 2009 Microchip Technology Inc.