PIC18F67J11-IPT Datasheet, PDF (313/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

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23.2 Voltage Reference Accuracy/Error
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 23-1) keep CVREF from approaching the refer-
ence source rails. The voltage reference is derived
from the reference source; therefore, the CVREF output
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
found in Section 27.0 “Electrical Characteristics”.
23.3 Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RF5 pin if the
CVROE bit is set. Enabling the voltage reference out-
put onto RA2 when it is configured as a digital input will
increase current consumption. Connecting RF5 as a
digital output with CVRSS enabled will also increase
current consumption.
The RF5 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage
reference output for external connections to VREF.
Figure 23-2 shows an example buffering technique.
23.4 Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
23.5 Effects of a Reset
A device Reset disables the voltage reference by
clearing CVREN (CVRCON<7>). This Reset also
disconnects the reference from the RA2 pin by clearing
CVROE, and selects the high-voltage range by clearing
CVRR. The CVR value select bits are also cleared.
FIGURE 23-2:
COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC18F87J11
CVREF
Module
R⁽¹⁾
Voltage
RF5
Reference
Output
Impedance
+
–
CVREF Output
Note 1: R is dependent upon the comparator voltage reference configuration bits, CVRCON<5> and CVRCON<3:0>.
TABLE 23-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
CVRCON⁽²⁾ CVREN CVROE CVRR CVRSS CVR3
CVR2
CVR1
CVR0
61
CM1CON
CON
COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0
58
CM2CON
CON
COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0
58
TRISA
TRISA7⁽¹⁾ TRISA6⁽¹⁾ TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
60
TRISF
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1
—
60
ANCON0⁽²⁾ PCFG7 PCFG6
—
PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
59
ANCON1⁽²⁾ PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8
59
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used with the comparator voltage reference.
Note 1: These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are
unimplemented.
2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
© 2009 Microchip Technology Inc.
DS39778D-page 313