PIC18F67J11-IPT Datasheet, PDF (190/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
14.2 Timer2 Interrupt
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match) pro-
vides the input for the 4-bit output counter/postscaler.
This counter generates the TMR2 match interrupt flag
which is latched in TMR2IF (PIR1<1>). The interrupt is
enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE (PIE1<1>).
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>).
FIGURE 14-1:
TIMER2 BLOCK DIAGRAM
4
T2OUTPS3:T2OUTPS0
2
T2CKPS1:T2CKPS0
FOSC/4
1:1, 1:4, 1:16
Prescaler
Internal Data Bus
Reset
TMR2
8
14.3 Timer2 Output
The unscaled output of TMR2 is available primarily to
the ECCPx/CCPx modules, where it is used as a time
base for operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP modules operating in SPI mode.
Additional information is provided in Section 19.0
“Master Synchronous Serial Port (MSSP) Module”.
1:1 to 1:16
Postscaler
TMR2/PR2
Match
Comparator
8
Set TMR2IF
TMR2 Output
(to PWM or MSSP)
PR2
8
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE TMR0IF INT0IF RBIF
57
PIR1
PMPIF ADIF
RC1IF
TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
60
PIE1
PMPIE ADIE
RC1IE
TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60
IPR1
PMPIP ADIP
TMR2⁽¹⁾ Timer2 Register
RC1IP
TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
60
58
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 58
PR2⁽¹⁾ Timer2 Period Register
58
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0.
DS39778D-page 190
© 2009 Microchip Technology Inc.