PIC18F67J11-IPT Datasheet, PDF (301/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
21.7 A/D Converter Calibration
The A/D Converter in the PIC18F87J11 family of
devices includes a self-calibration feature which com-
pensates for any offset generated within the module.
The calibration process is automated and is initiated by
setting the ADCAL bit (ADCON1<6>). The next time
the GO/DONE bit is set, the module will perform a
“dummy” conversion (that is, with reading none of the
input channels) and store the resulting value internally
to compensate for the offset. Thus, subsequent offsets
will be compensated. An example of a calibration
routine is shown in Example 21-1.
The calibration process assumes that the device is in a
relatively steady-state operating condition. If A/D
calibration is used, it should be performed after each
device Reset or if there are other major changes in
operating conditions.
21.8 Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed
mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT2:ACQT0 and
ADCS2:ADCS0 bits in ADCON1 should be updated in
accordance with the power-managed mode clock that
will be used. After the power-managed mode is entered
(either of the power-managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
mode clock source until the conversion has been com-
pleted. If desired, the device may be placed into the
corresponding power-managed Idle mode during the
conversion.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
Operation in the Sleep mode requires the A/D RC clock
to be selected. If bits, ACQT2:ACQT0, are set to ‘000’
and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEP instruction and entry to Sleep mode. The IDLEN
and SCS bits in the OSCCON register must have
already been cleared prior to starting the conversion.
EXAMPLE 21-1: SAMPLE A/D CALIBRATION ROUTINE
BSF
BCF
BCF
BSF
BSF
BSF
CALIBRATION
BTFSC
BRA
BCF
WDTCON,ADSHR
ANCON0,PCFG0
WDTCON,ADSHR
ADCON0,ADON
ADCON1,ADCAL
ADCON0,GO
ADCON0,GO
CALIBRATION
ADCON1,ADCAL
;Enable write/read to the shared SFR
;Make Channel 0 analog
;Disable write/read to the shared SFR
;Enable A/D module
;Enable Calibration
;Start a dummy A/D conversion
;
;Wait for the dummy conversion to finish
;
;Calibration done, turn off calibration enable
;Proceed with the actual A/D conversion
© 2009 Microchip Technology Inc.
DS39778D-page 301