PIC18F67J11-IPT Datasheet, PDF (77/448 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J11 FAMILY
TABLE 5-5: REGISTER FILE SUMMARY (PIC18F87J11 FAMILY)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on
Page:
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 57, 67
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000 57, 67
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000 57, 67
STKPTR
STKFUL STKUNF
—
SP4
SP3
SP2
SP1
SP0 00-0 0000 57, 68
PCLATU
—
—
bit 21⁽¹⁾ Holding Register for PC<20:16>
---0 0000 57, 67
PCLATH
Holding Register for PC<15:8>
0000 0000 57, 67
PCL
PC Low Byte (PC<7:0>)
0000 0000 57, 67
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000 57, 98
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000 57, 98
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000 57, 98
TABLAT
Program Memory Table Latch
0000 0000 57, 98
PRODH
Product Register High Byte
xxxx xxxx 57, 111
PRODL
Product Register Low Byte
xxxx xxxx 57, 111
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF 0000 000x 57, 115
INTCON2
RBPU
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP
INT3IP
RBIP 1111 1111 57, 115
INTCON3
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF 1100 0000 57, 115
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
57, 84
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
57, 85
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
57, 85
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
57, 85
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
N/A
value of FSR0 offset by W
57, 85
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte ---- xxxx 57, 84
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx 57, 84
WREG
Working Register
xxxx xxxx 57, 69
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
57, 84
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
57, 85
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
57, 85
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
57, 85
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
N/A
value of FSR1 offset by W
57, 85
FSR1H
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte ---- xxxx 57, 84
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx 57, 84
BSR
—
—
—
—
Bank Select Register
---- 0000 57, 72
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
58, 84
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
58, 85
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
58, 85
PREINC2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
58, 85
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
N/A
value of FSR2 offset by W
58, 85
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Bold indicates shared access SFRs.
Bit 21 of the PC is only available in Serial Programming modes.
Default (legacy) SFR at this address, available when WDTCON<4> = 0.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP modules are operating in I²C™ Slave mode. See Section 19.4.3.2
“Address Masking Modes” for details
These bits and/or registers are only available in 80-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 80-pin devices.
These bits are only available in select oscillator modes (FOSC2 Configuration bit = 0); otherwise, they are unimplemented.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different
functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
© 2009 Microchip Technology Inc.
DS39778D-page 77