C868_02 Datasheet, PDF (95/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
On-Chip Peripheral Components
SW
SEL
Correct
Hall Event
T13pm
T12pm
T12om
T12c1cm
write to
bitfield
MCMPS
with
STRMCM =
’1’
write by software
6
reset
O
R
set
R
O
R
A
N
D
no action
T12zm
T13zm
direct
MCMPS
MCMP
clear
6
to modulation
selection
SW
SYN
IDLE
Figure 4-30 Modulation Selection and Synchronization
Figure 4-30 shows the modulation selection for the multi-channel mode. The event that
triggers the update of bit field MCMP is chosen by SWSEL. If the selected switching
event occurs, the reminder flag R is set. This flag monitors the update request and it is
automatically reset when the update takes place. In order to synchronize the update of
MCMP to a PWM generated by T12 or T13, bit field SWSYN allows the selection of the
synchronization event, which leads to the transfer from MCMPS to MCMP. Due to this
structure, an update takes place with a new PWM period.
If it is explicitly desired, the update takes place immediately with the setting of flag R
when the direct synchronization mode is selected. The update can also be requested by
SW by writing to bit field MCMPS with the shadow transfer request bit STRMCM set. If
this bit is set during the write action to the register, the flag R is automatically set. By
using the direct mode and bit STRMCM, the update takes place completely under SW
control.
The possible HW request events are:
• a T12 period-match while counting up (T12pm)
• a T12 one-match while counting down (T12om)
• a T13 period-match (T13pm)
User’s Manual
4-51
V 0.4, 2002-01