C868_02 Datasheet, PDF (171/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
Reset and System Clock Operation
5.4
Clock Generation
The top-level view of the system clock generation of the C868 is shown in Figure 5-3.
XTAL1
XTAL2
On-Chip
Osc
PLL
f_{OSC clkin}
clkout ^fPLL
SDD
MUX
system
clock (f_SYS)
Figure 5-3 Block Diagram of the Clock Generation
5.5
PLL Operation
The PLL consists of a voltage controlled oscillator (VCO) with a feedback path. A divider
in the feedback path divides the VCO frequency down. The resulting frequency is then
compared to the externally applied frequency. The phase detection logic determines the
difference between the two clock signals and accordingly controls the frequency of the
VCO. During start-up, the VCO increases its frequency until the divided feedback clock
matches the external clock frequency. A lock detection logic monitors and signals this
condition. The phase detection logic continues to monitor the two clock signals and
adjusts the VCO clock if required.
The PLL provides mechanisms to detect a failure of the external clock and to bring the
C868 into a safe state in such a case. When the PLL loses the lock to the external clock,
either due to a break of the crystal or an external line, it generate an internal reset. The
PLLR flag in the SCUWDT register is set, this flag can only be reset by a hardware reset
or by software.
Due to this operation, the VCO clock of the PLL has a frequency which is a multiple of
the externally applied clock. The factor for this is controlled through the value applied to
the divider in the feedback path. That is why this factor is often called a multiplier,
although it actually controls a divider. This parameter called the feedback divider has a
fixed value N = 15.
When software power down mode is entered, the PLL is powered down.
User’s Manual
5-5
V 0.4, 2002-01