C868_02 Datasheet, PDF (182/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
Fail Save Mechanism
SCUWDT
SCU/Watchdog Control Register
7
6
5
4
-
PLLR
-
WDTR
r
rwh
r
rwh
[Reset value: 00_H]
3
2
1
0
WDTEOI WDTDIS
rw
rw
WDTRS
rw
WDTRE
rw
Field
WDTRE
WDTRS
WDTDIS
WDTEOI
WDTR
PLLR
-
Bits Typ Description
0
rw WDT Refresh Enable.
Active high. Set to enable a refresh of the watchdog
timer. Must be set before WDTRS.
1
rw WDT Refresh Start.
Active high. Set to start refresh operation on the
watchdog timer. Must be set after WDTRE.
2
rw WDT Disable.
Active high. Set by software and cleared by general
reset.
3
rw WDT End of Initialization.
Active high. Set by software and cleared by general
reset.
4
rwh WDT Reset Indication Bit.
Active high. Set by hardware when a watchdog timer
reset occurs. Cleared by reset or WDT_RFSH or
software.
6
rwh PLL Reset Indication Bit.
Active high. Set by hardware when PLL reset occurs.
Cleared by reset or software.
7,5 r reserved;
returns ’0’ if read; should be written with ’0’;
User’s Manual
6-4
V 0.4, 2002-01