C868_02 Datasheet, PDF (221/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
Interrupt System
cycle to ensure that the transition is recognized so that the corresponding interrupt
request flag will be set (see Figure 7-8). The external interrupt request flags will
automatically be cleared by the CPU when the service routine is called.
Figure 7-8 External Interrupt Detection
7.5
Interrupt Response Time
If an external interrupt is recognized, its corresponding request flag is set at S5P2 in
every machine cycle. The value is not polled by the circuitry until the next machine cycle.
If the request is active and conditions are right for it to be acknowledged, a hardware
subroutine call to the requested service routine will be the next instruction to be
executed. The call itself takes two cycles. Thus a minimum of three complete machine
cycles will elapse between activation and external interrupt request and the beginning of
execution of the first instruction of the service routine.
A longer response time would be obtained if the request was blocked by one of the three
previously listed conditions. If an interrupt of equal or higer priority is already in progress,
the additional wait time obviously depends on the nature of the other interrupt’s service
routine. If the instruction in progress is not in its final cycle, the additional wait time cannot
be more than 3 cycles since the longest instructions (MUL and DIV) are only 4 cycles
long; and, if the instruction in progress is RETI or a write access to registers IEN0, IEN1
or IP0 the additional wait time cannot be more than 5 cycles (a maximum of one more
User’s Manual
7-37
V 0.4, 2002-01