C868_02 Datasheet, PDF (51/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
On-Chip Peripheral Components
4.4
Port 1, Port 3 Circuitry
The pins of ports 1 and 3 are multifunctional. They are port pins and also serve to
implement special features as listed in Table 4-2. Figure 4-1 shows a functional
diagram of a typical bit latch and I/O buffer, which is the core of the I/O-ports. The bit
latch (one bit in the port’s SFR) is represented as a type-D flip-flop, which will clock in a
value from the internal bus in response to a "write-to-latch" signal from the CPU. The Q
output of the flip-flop is placed on the internal bus in response to a "read-latch" signal
from the CPU. The level of the port pin itself is placed on the internal bus in response to
a "read-pin" signal from the CPU. Some instructions that read from a port (i.e. from the
corresponding port SFR P1 and P3) activate the "read-latch" signal, while others activate
the "read-pin" signal.
Figure 4-1 shows a functional diagram of a port latch with alternate function.
Read
Latch
Alternate
Output
Function
Int. Bus
Write
to
Latch
Read
Pin
D
Q
Bit
Latch
CLK Q
Alternate
Input
Function
Figure 4-1 Ports 1 and 3
Port
Port
Driver
Pin
Circuit
User’s Manual
4-7
V 0.4, 2002-01