C868_02 Datasheet, PDF (168/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
Reset and System Clock Operation
The time required for a reset operation must be at least tbd - tbd usec. The same
considerations apply if the reset signal is generated externally (Figure 5-1 b). In each
case it must be assured that the logics at ALE/BSL, TXD and other testmode related
pins are latched properly.
V_DDP
a)
C868
RESET
b)
C868
&
RESET
V_DDP
c)
C868
RESET
Figure 5-1 Reset Circuitries
A correct reset leaves the processor in a defined state. The program execution starts at
location 0000_H. After reset is internally accomplished the port latches of ports 1 and 3
defaulted to FF_H, and they are set to input.
The contents of the internal RAM and XRAM of the C868 are not affected by a reset.
After power-up the contents are undefined, while it remains unchanged during a reset if
the power supply is not turned off.
5.2
Internal Reset after Power-On
Figure 5-2 shows the power-on sequence.
For the C868, the device enter into default reset state once RESET has gone low with
all I/O ports set to input or high impedance. The internal reset is released only after the
PLL has locked. In (Figure 5-2,II) the internal reset remains active even after the
RESET pin had gone high, the I/O ports 1 and 3 remain as input. In (Figure 5-2,III),
detection for continuous PLL lock is done before internal reset is released. The 4096
cycles of continuous lock detection ensures that a reset due to PLL unlock will not
happen during the transient period after the PLL started functioning. After continuous
PLL lock is detected, the C868 starts operation.(Figure 5-2,IV)
User’s Manual
5-2
V 0.4, 2002-01