C868_02 Datasheet, PDF (31/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
Memory Organization
bootstrap mode. Table 3-4 and Table 3-5 show the various memory configurations
respectively in an example.
Table 3-4 Normal XRAM Mode
Memory Space
Code Space
Data Space
Memory Boundary
XRAM: FF00_H to FFFF_H
ROM/RAM: 0000_H to 1FFF_H
Table 3-5 Bootstrap XRAM Mode
Memory Space
Code Space
Data Space
Memory Boundary
Boot ROM: 0000_H to 0FFF_H
XRAM: FF00_H to FFFF_H
RAM/ROM: 0000_H to 1FFF_H
The on-chip XRAM, which is in the upper part of the 64 KB data space, is always enabled
in this mode for code access irrespective of the XMAP0 bit. The external data space also
becomes code space.
The actual physical sizes of the various memory types as mentioned above are product
specific. In the C868, the external accesses are prohibited. For code spaces, appropriate
branch instructions must therefore be inserted.
The on-chip data space is accessible, as usual, via MOVX instructions. The on-chip data
memory accesses to RAM/ROM are restricted by the physical memory available in the
respective product. For the C868-1R, the option to disable the access to the ROM is
selectable upon request. This option is reflected in SFR Version bit 7(1 for access
disabled).
An exit from the XRAM mode is possible by software only. In this mode the on-chip
XRAM is disabled as data space irrespective of XMAP0 bit in SFR SYSCON0. It will
remain disabled after exit from XRAM mode unless the XMAP0 had been cleared prior
to entering this mode.
User’s Manual
3-7
V 0.4, 2002-01