C868_02 Datasheet, PDF (179/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
Fail Save Mechanism
6
Fail Save Mechanism
The C868 offers enhanced fail save mechanisms, which allow an automatic recovery
from software upset or hardware failure :
a programmable watchdog timer (WDT), with variable time-out period from 12.8 s to
819.2 s at f_SYS = 40 MHz.
6.1
Programmable Watchdog Timer
To protect the system against software failure, the user’s program has to clear this
watchdog within a previously programmed time period. lf the software fails to do this
periodical refresh of the watchdog timer, an internal reset will be initiated. The software
can be designed so that the watchdog times out if the program does not work properly.
lt also times out if a software error is based on hardware-related problems.
The watchdog timer in the C868 is a 16-bit timer, which is incremented by a count rate
of f_SYS/2 upto f_SYS/128. The machine clock of the C868 is divided by a prescaler, a divide-
by-two or a divide-by-128 prescaler. The upper 8 bits of the Watchdog Timer can be
preset to a user-programmable value via a watchdog service access in order to vary the
watchdog expire time. The lower 8 bits are reset on each service access. Figure 6-1
shows the block diagram of the watchdog timer unit.
f_SYS
DISWDT
WDT
Control
WDTREL
1:2
1:128
MUX
Clear
WDT Low Byte
WDTIN
WDT High Byte
WDTRST
Figure 6-1 Block Diagram of the Programmable Watchdog Timer
6.1.1 Register Definition of the Watchdog Timer
The current count value of the Watchdog Timer is contained in the Watchdog Timer
Register WDT, which is a non-bitaddressable read-only register. The operation of the
Watchdog Timer is controlled by its bitaddressable Watchdog Timer Control Register
User’s Manual
6-1
V 0.4, 2002-01