C868_02 Datasheet, PDF (227/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
Power Saving Modes
8.4
Slow Down Mode Operation
In some applications, where power consumption and dissipation are critical, the
controller might run for a certain time at reduced speed (e.g. if the controller is waiting
for an input signal). Since in CMOS devices there is an almost linear dependence of the
operating frequency and the power supply current, a reduction of the operating
frequency results in reduced power consumption.
The slow down mode is activated by setting the bit SD in SFR PCON. If the slow down
mode is enabled, the clock signals for the CPU and the peripheral units can be reduced
from 1/2 to 1/32 of the nominal system clock rate. The clock divider is described in the
Reset and System Clock Operation chapter. The controller actually enters the slow
down mode after a short synchronization period (max. two machine cycles). The slow
down mode is terminated by clearing bit SD.
The slow down mode can be combined with the idle mode by setting the IDLE and SD
bits in SFR PCON.
There are two ways to terminate the combined Idle and Slow Down Mode :
– The idle mode can be terminated by activation of any enabled interrupt. The CPU
operation is resumed, the interrupt will be serviced and the next instruction to be
executed after the RETI instruction will be the one following the instruction that had
set the bits IDLE and SD. Nevertheless the slow down mode keeps enabled and if
required has to be terminated by clearing the bit SD in the corresponding interrupt
service routine or at any point in the program where the user no longer requires the
slow-down mode power saving.
– The other possibility of terminating the combined idle and slow down mode is a
hardware reset.
User’s Manual
8-5
V 0.4, 2002-01