C868_02 Datasheet, PDF (104/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
On-Chip Peripheral Components
Note: While timer T12 is stopped, the internal clock divider is reset in order to ensure
reproducible timings and delays.
Note: The timer period, compare values, passive state selects bits and passive levels
bits for both timers are written to shadow registers and not directly to the actual
registers. Thus the values for a new output signal can be programmed without
disturbing the currently generated signal(s). The transfer from the shadow
registers to the actual registers is enabled by setting the respective shadow
transfer enable bit STEx.
If the transfer is enabled the shadow registers are copied to the respective
registers as soon as the associated timer reaches the value zero the next time
(being cleared in edge aligned mode or counting down from 1 in center aligned
mode). When timer T12 is operating in center aligned mode, it will also copy the
registers (if enabled by STE12) if it reaches the currently programmed period
value (counting up).
When a timer is stopped (TxR=’0’), the shadow transfer takes place immediately
if the corresponding bit STEx is set.
After the transfer the respective bit STEx is cleared automatically.
User’s Manual
4-60
V 0.4, 2002-01