C868_02 Datasheet, PDF (83/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
On-Chip Peripheral Components
CC6xS
T12_xST_so
Cap_xST_so
T12_xST_ro
hyst_x_ev
CC6xR
Hall_edge_o
hyst_x_state
O
R
A
N
D
O
R
A
N
D
set
Q
CC6xST
reset Q
OR
T12clk
CC6xPS
A
CC6x_
N
0 T12_o
D
1
COUT6x_
A
0 T12_o
N
1
D
COUT6xPS
DTCx_rl
DTCx_o
dead-time generation
Figure 4-17 T12 Logic for CC6xST Control
The events triggering the set and reset action of the CC6xST bits have to be combined,
see Figure 4-17. The occurrence of the selected capture event (signal Cap_xST_so) or
the setting of CC6xS in register CMPMODIF also leads to a set action of bit CC6xST,
whereas the negative edge at pin CCPOSx (in hysteresis-like mode, signal hyst_x_ev)
or the setting of bit CC6xR leads to reset action.
The set signal is only generated while bit CC6xST is reset, a reset can only take place
while the bit is set. This permits the OR-combination of the resulting set and reset signals
to one common signal (DTCx_rl) triggering the reload of the dead-time counter. It is only
triggered if bit CC6xST is changed, permitting a correct PWM generation with dead-time
and the complete duty cycle range of 0% to 100% in edge-aligned and in center-aligned
mode.
In the case that the dead-time generation is enabled, the change of bit CC6xST triggers
the dead-time unit and a signal DTCx_o is generated. The length of the ’0’ level of this
signal corresponds to the desired dead-time, which is used to delay the rising edge
(passive to active edge) of the output signal.
In order to generate independent PWM patterns for the highside and the lowside
switches of the power inverter, the interval when a PWM signal should be active can be
selected by the bits CC6xPS. They select if the PWM signal is active while the compare
state bit is ’0’ (T12 counter value below the compare value) or while it is ’1’ (T12 counter
value above the compare value).
User’s Manual
4-39
V 0.4, 2002-01