C868_02 Datasheet, PDF (137/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
On-Chip Peripheral Components
Register MCMCTR contains control bits for the multi-channel functionality.
MCMCTRLL
Multi-Channel Mode Control Register
7
6
5
4
3
[Reset value: 00_H]
2
1
0
-
-
SWSYN
-
r
r
rw
r
SWSEL
rw
Field
SWSEL
SWSYN
Bits Type Description
[2:0] rw
Switching Selection
Bitfield SWSEL selects one of the following trigger
request sources (next multi-channel event) for the
shadow transfer from MCMPS to MCMP. The trigger
request is stored in the reminder flag R until the
shadow transfer is done and flag R is cleared
automatically with the shadow transfer. The shadow
transfer takes place synchronously with an event
selected in bitfield SWSYN.
000 no trigger request will be generated
001 correct hall pattern on CCPOSx detected
010 T13 period-match detected (while counting up)
011 T12 one-match (while counting down)
100 T12 channel 1 compare-match detected
(phase delay function)
101 T12 period match detected (while counting up)
else reserved, no trigger request will be generated
[5:4] rw
Switching Synchronization
Bitfield SWSYN triggers the shadow transfer
between MCMPS and MCMP if it has been
requested before (flag R set by an event selected by
SWSEL). This feature permits the synchronization of
the outputs to the PWM source, that is used for
modulation (T12 or T13).
00 direct; the trigger event directly causes the
shadow transfer
01 T13 zero-match triggers the shadow transfer
10 a T12 zero-match (while counting up) triggers
the shadow transfer
11 reserved; no action
User’s Manual
4-93
V 0.4, 2002-01