C868_02 Datasheet, PDF (172/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
Reset and System Clock Operation
5.5.1 VCO Frequency Ranges
The frequency range for f_VCO is:
100 MHz f_VCO 160 MHz
[5-1]
5.5.2 K-Divider
The K-Divider is a software controlled divider. The bit field KDIV is provided in register
CMCON. Software can write to this field in order to change the PLL frequency f_PLL. The
default KDIV value is 4. Table 5-2 lists the possible values for KDIV and the resulting
division factor.
The divider is designed such that a synchronous switching of the clock is performed
without spurious or shortened clock pulses when software changes the divider factor
KDIV. However, special attention has to be paid concerning the effect of such a clock
change to the various modules in the system.
5.5.3 Determining the PLL Clock Frequency
This section gives the formulas for the determination of the PLL clock frequency. In PLL
operation, the PLL clock is derived from the VCO frequency f_VCO divided by the K-factor.
f_VCO is generated from the external clock multiplied by 15.
The PLL clock frequency f_PLL can be made proportional to the ratio 15 / K, where bit field
CMCON.KDIV determines the clock scale factor K. The VCO output frequency is
determined by:
f_VCO = 15 Ωf_OSC
[5.2]
and the resulting PLL clock is determined by:
f_PLL = f_VCO / K =
15
K
Ωf_OSC
[5.3]
Since stable operation of the VCO is only guaranteed if f_VCO remains inside of the
defined frequency range for the VCO (see Equation [5-1]), the external frequency f_OSC
is also confined to certain ranges. Table 5-1 list the range.
User’s Manual
5-6
V 0.4, 2002-01