C868_02 Datasheet, PDF (173/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
Reset and System Clock Operation
Table 5-1 Input Frequencies and N Factor=15 for f_VCO
f_VCO = 100 MHz
6.67
f_VCO = 160 MHz
10.67
Table 5-2 Output Frequencies f_PLL Derived from Various Output Factors
K-Factor
Selected KDIV
Factor
2
000_B
4
010_B
5¹⁾
011_B
6
100_B
8
101_B
9¹⁾
110_B
10
111_B
16
001_B
f_PLL
Duty
Jitter
f_VCO = f_VCO = ^{Cycle [%]}
100 MHz 160 MHz
50
80
50
25
40
50
20
32
40
16.67 26.67 50
linear depending on f_VCO
at f_VCO =100MHz: +/-300ps
at f_VCO =160MHz: +/-250ps
additional jitter for odd Kdiv
factors tbd.
12.5
20
50
11.11 17.78 44
10
16
50
6.25
10
50
1) _{These odd factors should not be used (not tested because off the unsymmetrical duty cycle).}
2) Shaded combinations should not be used because they are above the maximum CPU frequency of 40MHz.
User’s Manual
5-7
V 0.4, 2002-01