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C868_02 Datasheet, PDF (183/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller
C868
Fail Save Mechanism
6.1.2 Starting the Watchdog Timer
When the reset input to the Watchdog Timer, the Watchdog Timer is enabled. Once
disabled it cannot be stopped during active mode of the device. If the software fails to
clear the watchdog timer an internal reset will be initiated. The reset cause (external
reset or reset caused by the watchdog) can be examined by software (status flag WDTR
in SCUWDT is set). A refresh of the watchdog timer is done by setting bits WDTRE and
WDTRS (in SFR SCUWDT) consecutively. This double instruction sequence has been
implemented to increase system security.
It must be noted, however, that the watchdog timer is halted during the idle mode and
power-down mode of the processor (see section "Power Saving Modes"). It is not
possible to use the idle mode in combination with the watchdog timer function.
Therefore, even the watchdog timer cannot reset the device when one of the power
saving modes has been entered accidentally.
6.1.3 Refreshing the Watchdog Timer
At the same time the watchdog timer is started, the 8-bit register WDTH is preset by the
contents of WDTREL. Once started the watchdog cannot be stopped by software but can
only be refreshed to the reload value by first setting bit WDTRE and WDTRS (in SFR
SCUWDT) consecutively. Bit WDTR will automatically be cleared during the second
machine cycle after having been set. For this reason, setting WDTRS bit has to be a one
cycle instruction (e.g. SETB WDTRS). This double-instruction refresh of the watchdog
timer is implemented to minimize the chance of an unintentional reset of the watchdog.
The reload register WDTREL can be written to at any time, as already mentioned.
Therefore, a periodical refresh of WDTREL can be added to the above mentioned
starting procedure of the watchdog timer. Thus a wrong reload value caused by a
possible distortion during the write operation to the WDTREL can be corrected by
software.
User’s Manual
6-5
V 0.4, 2002-01