C868_02 Datasheet, PDF (132/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
On-Chip Peripheral Components
2) _{Bit PSL63 has a shadow register to allow for updates without undesired pulses on the output line. The bit is}
updated with the T13 shadow transfer. A read action targets the actually used values, whereas a write action
targets the shadow bits.
4.8.4.2 Multi-Channel Control
Register MCMOUTS contains bits controlling the output states for multi-channel mode.
Furthermore, the appropriate signals for the block commutation by Hall sensors can be
selected. This register is a shadow register (that can be written) for register MCMOUT,
which indicates the currently active signals.
MCMOUTSL
Multi-Channel Mode Output Shadow Register ,Low Byte
7
6
5
4
3
2
[Reset value: 00_H]
1
0
STRMCM
-
w
r
MCMPS
rw
Field
MCMPS
STRMCM
-
Bits Type Description
[5:0] rw Multi-Channel PWM Pattern Shadow
Bitfield MCMPS is the shadow bitfield for bitfield
MCMP. The multi-channel shadow transfer is
triggered according to the transfer conditions defined
by register MCMCTR.
7
w Shadow Transfer Request for MCMPS
Setting this bits during a write action leads to an
immediate update of bitfield MCMP by the value
written to bitfield MCMPS. This functionality permits
an update triggered by SW. When read, this bit
always delivers ’0’.
0 Bitfield MCMP is updated according to the
defined HW action. The write access to bitfield
MCMPS doesn’t modify bitfield MCMP.
1 Bitfield MCMP is updated by the value written
to bitfield MCMPS.
6
r
reserved;
returns ’0’ if read; should be written with ’0’;
User’s Manual
4-88
V 0.4, 2002-01