C868_02 Datasheet, PDF (220/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
Interrupt System
Table 7-3 Interrupt Source and Vectors
00ABH(EX19)
00D3_H(EX20)
00DB_H(EX21)
00E3_H(EX22)
Wake-up from power-down 007B_H
–
mode
1) _{Capture/compare has 10 interrupt sources channeled to the 4 interrupt nodes INP0..3. The 3 capture/compare}
ports has 3 pairs of interrupt request flags, ICC60R, ICC60F, ICC61R, ICC61F, ICC62R, ICC62F. The other
flags are T12OM, T12PM, T13CM, T13PM, TRPF, WHE, CHE.
Execution proceeds from that location until the RETI instruction is encountered. The
RETI instruction informs the processor that the interrupt routine is no longer in progress,
then pops the two top bytes from the stack and reloads the program counter. Execution
of the interrupted program continues from the point where it was stopped. Note that the
RETI instruction is very important because it informs the processor that the program left
the current interrupt priority level. A simple RET instruction would also have returned
execution to the interrupted program, but it would have left the interrupt control system
thinking an interrupt was still in progress. In this case no interrupt of the same or lower
priority level would be acknowledged.
External Interrupts
The external interrupts 0 and 1 can be programmed to be level-activated or negative-
transition activated by setting or clearing bit ITx (x = 0 or 1), respectively in register
TCON. If ITx = 0, external interrupt x is triggered by a detected low level at the INTx pin.
If ITx = 1, external interrupt x is negative edge-triggered. In this mode, if successive
samples of the INTx pin show a high in one cycle and a low in the next cycle, interrupt
request flag IEx in TCON is set. Flag bit IEx=1 then requests the interrupt.
If the external interrupt 0 or 1 is level-activated, the external source has to hold the
request active until the requested interrupt is actually generated. Then it has to
deactivate the request before the interrupt service routine is completed, or else another
interrupt will be generated.
The external interrupts 2 and 3 can be programmed to be negative or positive transition-
activated by setting or clearing bits I2FR or I3FR in register T2CON. If IxFR = 0 (x = 2
or 3) then the external interrupt x is negative transition-activated. If IxFR = 1, external
interrupt is triggered by a positive transition.
Since the external interrupt pins are sampled once in each machine cycle, an input high
or low should be held for at least 3 oscillator periods to ensure sampling. lf the external
interrupt is positive (negative) transition-activated, the external source has to hold the
request pin low (high) for at least one cycle, and then hold it high (low) for at least one
User’s Manual
7-36
V 0.4, 2002-01