C868_02 Datasheet, PDF (131/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
On-Chip Peripheral Components
Register PSLR defines the passive state level driven by the output pins of the module.
The passive state level is the value that is driven by the port pin during the passive state
of the output. During the active state, the corresponding output pin drives the active state
level, which is the inverted passive state level. The passive state level permits to adapt
the driven output levels to the driver polarity (inverted, not inverted) of the connected
power stage.
PSLRL
Passive State Level Register ,High Byte
7
6
5
4
3
[Reset value: 00_H]
2
1
0
PSL63
-
PSL
rwh
r
rwh
Field
PSL¹⁾
PSL63²⁾
-
Bits Type Description
[5:0] rwh Compare Outputs Passive State Level
The bits of this bitfield define the passive level driven
by the module outputs during the passive state. The
bit positions are:
bit 0 passive level for output CC60
bit 1 passive level for output COUT60
bit 2 passive level for output CC61
bit 3 passive level for output COUT61
bit 4 passive level for output CC62
bit 5 passive level for output COUT62
The value of each bit position is defined as:
0 The passive level is ’0’.
1 The passive level is ’1’.
7
rwh Passive State Level of Output COUT63
This bitfield defines the passive level of the output
pin COUT63.
0 The passive level is ’0’.
1 The passive level is ’1’.
6
r
reserved;
returns ’0’ if read; should be written with ’0’;
1) _{Bitfield PSL has a shadow registers to allow for updates without undesired pulses on the output lines. The bits}
are updated with the T12 shadow transfer. A read action targets the actually used values, whereas a write
action targets the shadow bits.
User’s Manual
4-87
V 0.4, 2002-01