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| C868_02 Datasheet, PDF (219/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller | |||
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C868
Interrupt System
Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine
cycle labeled C3 in Figure 7-7 then, in accordance with the above rules, it will be
vectored to during C5 and C6 without any instruction for the lower priority routine to be
executed.
Thus, the processor acknowledges an interrupt request by executing a hardware-
generated LCALL to the appropriate servicing routine. In some cases it also clears the
flag that generated the interrupt, while in other cases it does not; then this has to be done
by the userâs software. The hardware clears the external interrupt flags IE0 and IE1 only
if they were transition-activated. The hardware-generated LCALL pushes the contents of
the program counter onto the stack (but it does not save the PSW) and reloads the
program counter with an address that depends on the source of the interrupt being
vectored to, as shown in the following Table 7-3.
Table 7-3 Interrupt Source and Vectors
Interrupt Source
External Interrupt 0
Timer 0 Overflow
External Interrupt 1
Timer 1 Overflow
Serial Channel
Timer 2 Overflow
A/D Converter
External Interrupt 2
External Interrupt 3
CCU6 interrupt node 0
CCU6 interrupt node 1
CCU6 interrupt node 2
CCU6 interrupt node3
Interrupt Vector
Address(core
connections)
0003H(EX0)
000BH(ET0)
0013H(EX1)
001BH(ET1)
0023H(ES)
002BH(EX5)
0033H(EX6)
003BH(EX7)
0043H(EX8)
004BH(EX9)
0053H(EX10)
005BH(EX11)
0063H(EX12)
006BH(EX13)
0083H(EX14)
008BH(EX15)
0093H(EX16)
009BH(EX17)
00A3H(EX18)
Interrupt Request Flags
IE0
TF0
IE1
TF1
RI / TI
TF2
IADC
IEX2
IEX3
INP01)
INP11)
INP21)
INP31)
Userâs Manual
7-35
V 0.4, 2002-01
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