C868_02 Datasheet, PDF (119/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
On-Chip Peripheral Components
Field
STE12
CDIR
CTM
Bits Type Description
5
rh Timer T12 Shadow Transfer Enable
Bit STE12 enables or disables the shadow transfer of
the T12 period value, the compare values and passive
state select bits and levels from their shadow registers
to the actual registers if a T12 shadow transfer event
is detected. Bit STE12 is cleared by hardware after the
shadow transfer.
A T12 shadow transfer event is a period-match while
counting up or a one-match while counting down.
0 The shadow register transfer is disabled.
1 The shadow register transfer is enabled.
6
rh Count Direction of Timer T12
This bit is set/reset according to the counting rules of
T12.
0 T12 counts up.
1 T12 counts down.
7
rw T12 Operating Mode
0 Edge-aligned Mode:
T12 always counts up and continues counting
from zero after reaching the period value.
1 Center-aligned Mode:
T12 counts down after detecting a period-match
and counts up after detecting a one-match.
1) _{A concurrent set/reset action on T12R (from T12SSC, T12RR or T12RS) will have no effect. The bit T12R will}
remain unchanged.
Note: A write action to the bit fields T12CLK or T12PRE is only taken into account while
the timer T12 is not running (T12R=0).
User’s Manual
4-75
V 0.4, 2002-01