C868_02 Datasheet, PDF (26/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
Memory Organization
3.1
Program Memory, “Code Space”
The C868-1S has 8 Kbytes of random access program memory (RAM) and 4 Kbytes of
Boot and Self Test ROM. In the normal mode the C868-1S executes program code out
of the internal RAM.
The Boot ROM includes a bootstrap loader program for the bootstrap loader of the C868-
1S. The software routines of the bootstrap loader program allow the easy and quick
programming or loading of the internal program RAM via the serial interface while the
MCU is in-circuit.
The C868-1R has 8Kbytes of ROM and 4 Kbytes of Self Test ROM.
The Self Test ROM has a self test program for the self test mode of the C868.
3.2
Data Memory, “Data Space”
The data memory address space consists of an internal and an external(XRAM) memory
space. The internal data memory is divided into three physically separate and distinct
blocks: the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128 byte
special function register (SFR) area.
While the upper 128 bytes of data memory and the SFR area share the same address
locations, they are accessed through different addressing modes. The lower 128 bytes
of data memory can be accessed through direct or register indirect addressing; the upper
128 bytes of RAM can be accessed through register indirect addressing only; the special
function registers are accessible through direct addressing. Four 8-register banks, each
bank consisting of eight 8-bit multi-purpose registers, occupy locations 00_H through 1F_H
in the lower RAM area. The next 16 bytes, locations 20_H through 2F_H, contain 128
directly addressable bit locations. The stack can be located anywhere in the internal data
memory address space, and the stack depth can be expanded up to 256 bytes.
The internal XRAM is located in the in the external data memory area and must be
accessed by external data memory instructions (MOVX).
3.2.1 General Purpose Registers
The lower 32 locations of the internal RAM are assigned to four banks with eight general
purpose registers (GPRs) each. Only one of these banks may be enabled at a time. Two
bits in the program status word, RS0 and RS1, select the active register bank. This
allows fast context switching, which is useful when entering subroutines or interrupt
service routines.
The 8 general purpose registers of the selected register bank may be accessed by
register addressing. With register addressing the instruction opcode indicates which
register is to be used. For indirect addressing R0 and R1 are used as pointer or index
register to address internal or external memory (e.g. MOV @R0).
User’s Manual
3-2
V 0.4, 2002-01