C868_02 Datasheet, PDF (192/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
7.2
Interrupt Registers
Interrupt System
7.2.1 Interrupt Enable Registers
Each interrupt vector can be individually enabled or disabled by setting or clearing the
corresponding bit in the interrupt enable registers IEN0, IEN1, IEN2. Register IEN0 also
contains the global disable bit (EA), which can be cleared to disable all interrupts at once.
Generally, after reset all interrupt enable bits are set to 0. That means that the
corresponding interrupts are disabled.
The SFR IEN0 contains the enable bits for the external interrupts 0 and 1, the timer
interrupts, and the UART interrupt.
IEN0
Interrupt Enable Register 0
[Reset value: 0X000000_B]
AF_H
AE_H
AD_H
AC_H
AB_H
AA_H
A9_H
A8_H
EA
-
ET2
ES
ET1
EX1
ET0
EX0
rw
r
rw
rw
rw
rw
rw
rw
Field
EA
ET2
ES
ET1
EX1
ET0
Bits Typ Description
0
rw Enable/disable all interrupts.
If EA=0, no interrupt will be acknowledged.
If EA=1, each interrupt source is individually enabled
or disabled by setting or clearing its enable bit.
1
rw Timer 2 overflow / external reload interrupt
enable.
If ET2 = 0, the timer 2 interrupt is disabled.
If ET2 = 1, the timer 2 interrupt is enabled.
2
rw Serial channel (UART) interrupt enable
If ES = 0, the serial channel interrupt 0 is disabled.
If ES = 1, the serial channel interrupt 0 is enabled.
3
rw Timer 1 overflow interrupt enable.
If ET1 = 0, the timer 1 interrupt is disabled.
If ET1 = 1, the timer 1 interrupt is enabled.
4
rw External interrupt 1 enable.
If EX1 = 0, the external interrupt 1 is disabled.
If EX1 = 1, the external interrupt 1 is enabled.
5
rw Timer 0 overflow interrupt enable.
If ET0 = 0, the timer 0 interrupt is disabled.
If ET0 = 1, the timer 0 interrupt is enabled.
User’s Manual
7-8
V 0.4, 2002-01