C868_02 Datasheet, PDF (163/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
On-Chip Peripheral Components
4.11
Conversion and Sample Time Control
The conversion and sample times are programmed via the bit fields ADCTC and ADSTC
respectively of the register ADCON1. Bit field ADCTC (conversion time control) selects
the internal ADC clock - adc_clk. Bit field ADSTC (sample time control) selects the
sample time. The data in ADCTC and ADSTC can be modified while a conversion is in
progress, but will only be evaluated after the current conversion has completed. Thus
the change will only affect the subsequent conversion. The internal ADC clock, adc_clk
is derived from the peripheral clock f_sys according to :
adc_clk = f_SYS / clock divider
Please note that the clock divider must be selected such that adc_clk does not exceed
2MHz.
The A/D conversion procedure is divided into four parts :
Synchronizing phase (t_SYNC), delay before actual conversion commence.
Sample phase (t_S), used for sampling the analog input voltage.
Conversion phase (t_CO), used for the real A/D conversion (includes calibration).
Write result phase (t_WR), used for writing the conversion result into the ADDAT registers.
The total A/D conversion time is defined by t_ADCC which is the sum of the four phase
periods, t_SYNC, t_S ,t_CO and t_WR. T_ADCC is computed with the following formula:
t_ADCC = 4/f_SYS + t_S + 8.5/adc_clk
The sample time t_S is configured in periods of the selected internal ADC clock. The table
below lists the possible combinations.
ADCTC
00 (default)
01
10
11
Clock
Divider
(TVC)
32
20
16
12
ADC Basic Clock
adc_clk
f_SYS / 32
f_SYS / 20
f_SYS / 16
f_SYS / 12
ADSTC
00 (default)
01
10
11
Sample Time t_S
(Periods of
adc_clk, STC)
2
4
8
16
User’s Manual
4-119
V 0.4, 2002-01