C868_02 Datasheet, PDF (204/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
Interrupt System
Field
CHE²⁾
WHE³⁾
IDLE⁴⁾
-
Bits Type Description
4
rh Correct Hall Event
0 A transition to a correct (=expected) hall event
has not yet been detected since this bit has
been reset for the last time.
1 A transition to a correct (=expected) hall event
has not yet been detected.
5
rh Wrong Hall Event
0 A transition to a wrong hall event (not the
expected one) has not yet been detected since
this bit has been reset for the last time.
1 A transition to a wrong hall event (not the
expected one) has been detected.
6
rh IDLE State
This bit is set together with bit WHE (wrong hall
event) and it has to be reset by SW.
0 No action.
1 Bitfield MCMP is cleared, the selected outputs
are set to passive state.
7
r
reserved;
returns ’0’ if read; should be written with ’0’;
1) _{During the trap state, the selected outputs are set to the passive state. The logic level driven during the passive}
state is defined by the corresponding bit in register CCMCON. Bit TRPS=’1’ and TRPF=’0’ can occur if the trap
condition is no longer active but the selected synchronization has not yet taken place.
2) _{On every valid hall edge the contents of CURH is compared with the pattern on pin CCPOSx and if equal bit}
CHE is set.
3) _{On every valid hall edge the contents of EXPH is compared with the pattern on pin CCPOSx. If both compares}
(CURH and EXPH with CCPOSx) are not true, bit WHE (wrong hall event) is set.
4) _{Bit field MCMP is hold to ’0’ by hardware as long as IDLE = ’1’.}
Note: Not all bits in register IS can generate an interrupt. Other status bits have been
added, which have a similar structure for their set and reset actions.
Note: The interrupt generation is independent from the value of the bits in register IS,
e.g. the interrupt will be generated (if enabled) even if the corresponding bit is
already set. The trigger for an interrupt generation is the detection of a set
condition (by HW or SW) for the corresponding bit in register IS.
Note: In compare mode (and hall mode), the timer-related interrupts are only generated
while the timer is running (TxR=1). In capture mode, the capture interrupts are also
generated while the timer T12 is stopped.
User’s Manual
7-20
V 0.4, 2002-01