C868_02 Datasheet, PDF (128/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
On-Chip Peripheral Components
The register TRPCTR controls the trap functionality. It contains independent enable bits
for each output signal and control bits to select the behavior in case of a trap condition.
The trap condition is a low level on the CTRAP input pin, which is monitored (inverted
level) by bit TRPF (in register IS). While TRPF=’1’ (trap input active), the trap state bit
TRPS (in register IS) is set to ’1’.
TRPCTRL
Trap Control Register ,Low Byte
[Reset value: 00_H]
7
6
5
4
3
2
1
0
-
-
-
-
-
TRPM2 TRPM1 TRPM0
r
r
r
r
r
rw
rw
rw
Field
TRPM1,
TRPM0
Bits Type Description
[1:0] rw
Trap Mode Control Bits 1, 0
These two bits define the behavior of the selected
outputs when leaving the trap state after the trap
condition has become inactive again.
A synchronization to the timer driving the PWM
pattern permits to avoid unintended short pulses
when leaving the trap state. The combination
(TRPM1, TRPM0) leads to:
00 The trap state is left (return to normal
operation according to TRPM2) when a zero-
match of T12 (while counting up) is detected
(synchronization to T12).
01 The trap state is left (return to normal
operation according to TRPM2) when a zero-
match of T13 is detected (synchronization to
T13).
10 reserved
11 The trap state is left (return to normal
operation according to TRPM2) immediately
without any synchronization to T12 or T13.
User’s Manual
4-84
V 0.4, 2002-01