C868_02 Datasheet, PDF (124/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
On-Chip Peripheral Components
Register TCTR4 allows the SW control of the run bits T12R and T13R by independent
set and reset conditions. Furthermore, the timers can be reset (while running) and the
bits STE12 and STE13 can be controlled by SW.
TCTR4L
Timer Control Register 4,Low Byte
[Reset value: 00_H]
7
6
5
4
3
2
1
0
T12STD T12STR
-
w
w
r
-
DTRES T12RES T12RS T12RR
r
w
w
w
w
Field
T12RR
T12RS
T12RES
DTRES
T12STR
T12STD
-
Bits Type Description
0
w Timer T12 Run Reset
Setting this bit resets the T12R bit.
0 T12R is not influenced.
1 T12R is cleared, T12 stops counting.
1
w Timer T12 Run Set
Setting this bit sets the T12R bit.
0 T12R is not influenced.
1 T12R is set, T12 starts counting.
2
w Timer T12 Reset
0 No effect on T12.
1 The T12 counter register is reset to zero. The
switching of the output signals is according to
the switching rules. Setting of T12RES has no
impact on bit T12R.
3
w Dead-Time Counter Reset
0 No effect on the dead-time counters.
1 The three dead-time counter channels are reset
to zero.
6
w Timer T12 Shadow Transfer Request
0 No action
1 STE12 is set, enabling the shadow transfer.
7
w Timer T12 Shadow Transfer Disable
0 No action
1 STE12 is reset without triggering the shadow
transfer.
[5:4] r
reserved;
returns ’0’ if read; should be written with ’0’;
User’s Manual
4-80
V 0.4, 2002-01