C868_02 Datasheet, PDF (102/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
On-Chip Peripheral Components
4.7.7 Interrupt Generation
The interrupt structure is shown in Figure 4-36. The interrupt event or the corresponding
interrupt set bit (in register ISS) can trigger the interrupt generation. The interrupt pulse
is generated independently from the interrupt flag in register IS. The interrupt flag can be
reset by SW by writing to the corresponding bit in register ISR.
If enabled by the related interrupt enable bit in register IEN, an interrupt pulse can be
generated at one of the four interrupt output lines of the module (length 2 clock cycles).
If more than one interrupt source is connected to the same interrupt node pointer (in
register INP), the requests are combined to one common line.
int_reset_SW
int_flag
INP
int_event
O
to I0
int_set_SW
R
int_enable
A
N
D
O
R
to I1
to I2
to I3
other interrupt sources
on the same INP
Figure 4-36 Interrupt Generation
4.7.8 Module Powerdown
The CCU6 is disabled when the chip goes into the powerdown mode as describe in . Or
it can be individually disabled by setting CCUDIS in register PMCON1. This helps to
reduce current consumption in the normal, slow down and idle modes of operation if the
CCU6 is not utilized. Bit CCUST in register PMCON2 reflects the powerdown status of
CCU6.
User’s Manual
4-58
V 0.4, 2002-01