C868_02 Datasheet, PDF (228/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

C868
Power Saving Modes
8.5
Software Power Down Mode
In the software power down mode, the on-chip oscillator which operates with the XTAL
pins and the PLL are all stopped. Therefore, all functions of the microcontroller are
stopped and only the contents of the on-chip RAM, XRAM and the SFR’s are maintained.
The port pins, which are controlled by their port latches, output the values that are held
by their SFR’s. The port pins which serve the alternate output functions show the values
they had at the end of the last cycle of the instruction which initiated the power down
mode. ALE is held at logic level high unless it is disabled.
In the power down mode of operation, V_DDC and V_DDP can be reduced to minimize power
consumption. It must be ensured, however, that V_DDC and V_DDP is not reduced before the
power down mode is invoked, and that V_DDC and V_DDP is restored to its normal operating
level before the power down mode is terminated. However, V_DDC cannot be lower than
V_DDP by more than 1(tbd) volt.
The software power down mode can be left either by an active reset signal or by a low
signal at one of the wake-up source pins. Using reset to leave power down mode puts
the microcontroller with its SFRs into the reset state. Using either the INT0 pin or the
RXD pin for power down mode exit starts the on-chip oscillator and the PLL and
maintains the state of the SFRs, which have been frozen when power down mode is
entered. Leaving power down mode should not be done before V_DDC and V_DDP is restored
to its nominal operating level.
The software power down mode is entered by setting bit PDE (PCON.1).
Note: Before entering the power down mode, an A/D conversion in progress must be
stopped.
8.5.1 Exit from Software Power Down Mode
If power down mode is exit via a hardware reset, the microcontroller with its SFRs is put
into the hardware reset state and the content of RAM and XRAM are not changed. The
reset signal that terminates the power down mode also restarts the on-chip oscillator and
the PLL. The reset operation should not be activated before V_DDC and V_DDP is restored to
its normal operating level.
Figure 8-1 shows the behaviour when power down mode is left via the INT0 or the RXD
wake-up capability.
User’s Manual
8-6
V 0.4, 2002-01