English
Language : 

C868_02 Datasheet, PDF (36/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller
◁
C868
Memory Organization
Table 3-6 Special Function Registers - Functional Blocks (cont’d)
Block Symbol
Name
Add- Contents
ress after
Reset
Cap- T12L
Timer T12 Counter Register, Low Byte ECH 00H
ture/ T12H
Timer T12 Counter Register, High Byte EDH 00H
Com- T13L
Timer T13 Counter Register, Low Byte EEH 00H
pare T13H
Timer T13 Counter Register, High Byte EFH 00H
Unit T12PRL
Timer T12 Period Register, Low Byte DEH 00H
T12PRH
Timer T12 Period Register, High Byte DFH 00H
T13PRL
Timer T13 Period Register, Low Byte D2H 00H
T13PRH
Timer T13 Period Register, High Byte D3H 00H
CC60RL
Capture/Compare Ch 0 Reg, Low Byte C2H 00H
CC60RH
Capture/Compare Ch 0 Reg, High Byte C3H 00H
CC61RL
Capture/Compare Ch 1 Reg, Low Byte C4H 00H
CC61RH
Capture/Compare Ch 1 Reg, High Byte C5H 00H
CC62RL
Capture/Compare Ch 2 Reg, Low Byte C6H 00H
CC62RH
Capture/Compare Ch 2 Reg, High Byte C7H 00H
CC63RL
T13 Compare Register, Low Byte
D4H 00H
CC63RH
T13 Compare Register, High Byte
D5H 00H
T12DTCL
Timer T12 Dead Time Ctrl, Low Byte E6H 00H
T12DTCH
Timer T12 Dead Time Ctrl, High Byte E7H 00H
CMPSTATL Compare Timer Status, Low Byte
F4H 00H
CMPSTATH Compare Timer Status, High Byte
F5H 00H
CMPMODIFL Compare Timer Modification, Low Byte EAH 00H
CMPMODIFH Compare Timer Modification, High Byte EBH 00H
TCTR0L
Timer Control Register 0, Low Byte
E2H 00H
TCTR0H
Timer Control Register 0, High Byte
E3H 00H
TCTR2L3)
Timer Control Register 2, Low Byte
F2H 00H
TCTR4L4)
Timer Control Register 4, Low Byte
F2H 0H
TCTR4H4)
Timer Control Register 4, High Byte
F3H 00H
ISL
Cap/Com Interrupt Register, Low Byte E4H 00H
ISH
Cap/Com Interrupt Register, High Byte E5H 00H
ISSL4)
Cap/Com Int Status Set Reg, Low Byte BCH 00H
ISSH4)
Cap/Com Int Status Set Reg, High Byte BDH 00H
ISRL3)
Cap/Com Int Status Reset Reg, Low Byte BCH 00H
ISRH3)
Cap/Com Int Status Reset Reg,High Byte BDH 00H
1) Bit-addressable special function registers
2) “X“ means that the value is undefined and the location is reserved
3) Register is mapped by bit RMAP in SYSCON0.4=1
4) Register is mapped by bit RMAP in SYSCON0.4=0
User’s Manual
3-12
V 0.4, 2002-01
 ▷