C868_02 Datasheet, PDF (196/244 Pages) Infineon Technologies AG – 8 - Bit CMOS Microcontroller

Field
TF0
TF1
C868
Interrupt System
Bits Typ Description
5
rwh Timer 0 overflow flag
Set by hardware on timer/counter 0 overflow.
Cleared by hardware when processor vectors to
interrupt routine.
7
rwh Timer 1 overflow flag
Set by hardware on timer/counter 1 overflow.
Cleared by hardware when processor vectors to
interrupt routine.
The timer 0 and timer 1 interrupts are generated by TF0 and TF1 in register TCON,
which are set by a rollover in their respective timer/counter registers. When a timer
interrupt is generated, the flag that generated it is cleared by the on-chip hardware when
the service routine is vectored to.
The external interrupts 0 and 1 (CCPOS0/T2/INT0/AN0 ,CCPOS1/T2EX/INT1/AN1)
can each be either level-activated or negative transition-activated, depending on bits IT0
and IT1 in register TCON. The flags that actually generate these interrupts are bits IE0
and lE1 in TCON. When an external interrupt is generated, the flag that generated this
interrupt is cleared by the hardware when the service routine is vectored to, but only if
the interrupt was transition-activated. lf the interrupt was level-activated, then the
requesting external source directly controls the request flag, rather than the on-chip
hardware.
IRCON0
External Interrupt Control Register 0
[Reset value: XXXXXX00_B]
7
6
5
4
3
2
1
0
-
-
-
-
-
-
EXINT3 EXINT2
r
r
r
r
r
r
rwh
rwh
Field
EXINT2
Bits Typ Description
0
rwh Interrupt Request Flag for External Interrupt 2
0 : Interrupt request is not active, cleared by
software. (default)
1 : Interrupt request is active, set by hardware.
User’s Manual
7-12
V 0.4, 2002-01